Altera Avalon Verification IP Suite Bedienungsanleitung PDF herunterladen (Seite 111)

signal_response_complete

signal_response_completePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Triggers when either signal_read_response_complete or signal_write_

response_complete is triggered. Indicates that either a read or a write

response was received and inserted into the response queue.

Description:

Verilog HDLLanguage support:

signal_transaction_fifo_overflow

signal_transaction_fifo_overflowPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Notifies the testbench that the FIFO is full and further transactions are

dropped.

Description:

Verilog HDLLanguage support:

signal_transaction_fifo_threshold

signal_transaction_fifo_thresholdPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Notifies the testbench that the transaction FIFO threshold level has exceeded.Description:

Verilog HDLLanguage support:

Altera Corporation

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