Altera Avalon Verification IP Suite Bedienungsanleitung PDF herunterladen (Seite 188)

set_min_instruction_queue_size()

void set_min_instruction_queue_size(int size).Prototype:

Verilog HDL: int size

VHDL: int size, bfm_id, req_if(bfm_id)

Arguments:

voidReturns:

Sets the pending instruction queue size minimum threshold.Description:

Verilog HDL, VHDLLanguage support:

set_min_result_queue_size()

void set_min_result_queue_size(int size).Prototype:

Verilog HDL: int size

VHDL: int size, bfm_id, req_if(bfm_id)

Arguments:

voidReturns:

Sets the pending result queue size minimum threshold.Description:

Verilog HDL, VHDLLanguage support:

set_result_timeout()

void set_result_timeout()Prototype:

Verilog HDL: int timeout

VHDL: int timeout, bfm_id, req_if(bfm_id)

Arguments:

voidReturns:

Sets the timeout value for a result. Set the value to 0 to disable timeout.Description:

Verilog HDL, VHDLLanguage support:

signal_unexpected_result_received

signal_unexpected_result_receivedPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that a result has been received without an instruction.Description:

Verilog HDLLanguage support:

Altera Corporation

Nios II Custom Instruction Master BFM

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set_min_instruction_queue_size()

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Altera Avalon Verification IP Suite Bedienungsanleitung Seite 188