Altera RapidIO II MegaCore Function Bedienungsanleitung Seite 92
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4–50 Chapter 4: Functional Description
Logical Layer Interfaces
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
Table 4–25 and Table 4–26 list the required format of the TX header information on the
gen_tx_data
bus for both device ID widths. The required format derives directly from
the RapidIO specification. You must include the header information in the clock cycle
in which you assert
gen_tx_startofpacket
. Note that the ackID field is filled by the IP
core, and the eight-bit device ID fields are not extended with zeroes, in contrast to the
destinationID and source ID fields in
gen_rx_hd_data
.
gen_tx_startofpacket
Input
Marks the active cycle containing the start of the packet. The user logic asserts
gen_tx_startofpacket
and
gen_tx_valid
to indicate that a packet is
available for the IP core to sample.
(1)
gen_tx_endofpacket
Input Marks the active cycle containing the end of the packet.
(1)
gen_tx_data[127:0]
Input
A 128-bit wide data bus. Carries the bulk of the information transferred from the
source to the sink.
(1)
The RapidIO II IP core fills in the RapidIO packet
ackID
field and adds the CRC
bits and padding bytes, but otherwise copies the bits from
gen_tx_data
to the
RapidIO packet without modifying them. Therefore, you must pack the
appropriate RapidIO packet fields in the correct RapidIO packet format in the
most significant bits of the
gen_tx_data
bus,
gen_tx_data[127:N]
. The
total width (127 – N + 1) of the header fields depends on the transaction and the
device ID width, as shown in Table 4–26 on page 4–51, and in “Pass-Through
Interface Usage Examples” on page 4–56.
gen_tx_empty[3:0]
Input
This bus identifies the number of empty bytes on the final data transfer of the
packet, which occurs during the clock cycle when
gen_tx_endofpacket
is
asserted.
(1)
The number of empty bytes must always be even.
gen_tx_packet_size[8:0]
(2)
Input
Indicates the number of valid bytes in the packet being transferred. The IP core
samples this signal only while
gen_tx_startofpacket
is asserted. User logic
must ensure this signal is correct while
gen_tx_startofpacket
is asserted.
Notes to Table 4–24:
(1)
gen_tx_valid
is used to qualify all the other input signals of the transmit side of the Avalon-ST pass-through interface.
(2) This signal is not defined in the Avalon Interface Specifications. However, it refers to data being transferred on the Avalon-ST sink interface.
Table 4–24. Avalon-ST Pass-Through Interface Transmit Side (Avalon-ST Sink) Signals (Part 2 of 2)
Signal Name Type Function
Table 4–25. RapidIO Header Information Format on gen_tx_data Bus
Field
gen_tx_data Bits
Device ID Width 8 Device ID Width 16
ackID[5:0]
[127:122] [127:122]
VC
[121] [121]
CRF
[120] [120]
prio[1:0]
[119:118] [119:118]
tt[1:0]
[117:116] [117:116]
ftype[3:0]
[115:112] [115:112]
destinationID[<deviceIDwidth>–1:0]
[111:104] [111:96]
sourceID[<deviceIDwidth>–1:0]
[103:96] [95:80]
specific_header
[95:...] [79:...]
- User Guide 1
- RapidIO II MegaCore Function 1
- Contents 3
- Contents v 5
- Chapter 5. Signals 6
- Chapter 6. Software Interface 6
- Chapter 7. Testbench 6
- 1. About The RapidIO II 9
- MegaCore Function 9
- Releases 10
- RapidIO II IP Core Features 10
- Features 11
- Device Family Support 12
- IP Core Verification 13
- Hardware Testing 14
- Interoperability Testing 14
- Note to Table 1–3: 16
- Notes to Table 1–4: 16
- Installation and Licensing 17
- 2. Getting Started 19
- Simulating IP Cores 22
- Transceiver Settings 26
- External Transceiver PLL 26
- 3. Parameter Settings 31
- Note to Table 3–1: 32
- Enable 16-Bit Device ID Width 33
- Logical Layer Settings 34
- Capability Registers Settings 35
- Device ID 36
- Vendor ID 36
- Revision ID 36
- Assembly ID 36
- Assembly Information CAR 37
- Enable Flow Control Support 38
- Enable Switch Support 38
- Number of Ports 38
- Port Number 39
- Maximum PDU 39
- Destination Operations CAR 40
- Port General Control CSR 40
- Port 0 Control CSR 41
- Lane n Status 0 CSR 41
- Extended Features Pointer CSR 41
- 4. Functional Description 43
- Note to Table 4–2: 44
- Clocking and Reset Structure 45
- Notes to Table 4–3: 46
- RapidIO II 47
- Transactions 55
- Notes to Table 4–6: 57
- Notes to Table 4–7: 59
- Note to Table 4–8: 59
- Note to Figure 4–9: 66
- Note to Table 4–10: 70
- Notes to Table 4–11: 71
- Table 6–60 on page 6–40 72
- Note to Table 4–12: 73
- Maintenance Module 74
- Maintenance Interface Signals 75
- Doorbell Module Block Diagram 86
- Preserving Transaction Order 87
- Doorbell Module Signals 88
- Generating a Doorbell Message 88
- Receiving a Doorbell Message 89
- Transaction ID Ranges 90
- Notes to Table 4–24: 92
- Note to Table 4–26: 94
- Note to Table 4–27: 95
- field 97
- User Receiving Write Request 100
- Logical Layer Interfaces 101
- Transport Layer 112
- Receiver 113
- Transmitter 114
- Physical Layer 115
- Physical Layer Interfaces 116
- Low-level Interface Receiver 116
- CRC Checking and Removal 117
- Protocol Violations 119
- Fatal Errors 119
- Maintenance Avalon-MM Slave 120
- Maintenance Avalon-MM Master 121
- Port-Write Reception Module 122
- Input/Output Avalon-MM Slave 122
- Input/Output Avalon-MM Master 123
- 5. Signals 125
- Physical Layer Signals 126
- Low Latency Signals 127
- Multicast Event Signals 128
- Chapter 5: Signals 5–5 129
- Note to Table 5–7: 130
- Chapter 5: Signals 5–7 131
- 5–8 Chapter 5: Signals 132
- Register-Related Signals 133
- Avalon-MM Interface Signals 133
- Note to Table 5–12: 134
- Chapter 5: Signals 5–11 135
- Note to Table 5–15: 136
- Error Reporting Signals 137
- 5–14 Chapter 5: Signals 138
- 6. Software Interface 139
- Memory Map 140
- Physical Layer Registers 144
- Note to Table 6–9: 147
- Note to Table 6–14: 154
- Note to Table 6–15: 158
- Note to Table 6–17: 160
- Note to Table 6–22: 164
- Note to Table 6–23: 164
- Note to Table 6–24: 165
- Note to Table 6–25: 165
- Note to Table 6–26: 166
- Note to Table 6–27: 167
- Notes to Table 6–28: 168
- Notes to Table 6–29: 169
- Note to Table 6–30: 169
- Note to Table 6–31: 169
- Notes to Table 6–32: 170
- Note to Table 6–34: 171
- Note to Table 6–35: 171
- Note to Table 6–36: 172
- Note to Table 6–37: 172
- Transmit Port-Write Registers 174
- Receive Port-Write Registers 175
- Note to Table 6–59: 178
- Error Management Registers 180
- Note to Table 6–66: 181
- Notes to Table 6–67: 183
- Notes to Table 6–70: 185
- Notes to Table 6–71: 185
- Doorbell Message Registers 191
- Note to Table 6–89: 193
- 7. Testbench 195
- 7–2 Chapter 7: Testbench 196
- Testbench Overview 196
- Testbench Sequence 197
- 7–4 Chapter 7: Testbench 198
- Chapter 7: Testbench 7–5 199
- SWRITE Transactions 200
- NREAD Transactions 200
- NWRITE_R Transactions 201
- NWRITE Transactions 202
- Doorbell Transactions 202
- Port-Write Transactions 203
- Testbench Completion 204
- Chapter 7: Testbench 7–11 205
- 7–12 Chapter 7: Testbench 206
- A. Initialization Sequence 207
- MegaCore Function v12.1 209
- Additional Information 213
- Info–2 Additional Information 214
- Document Revision History 214
- Additional Information Info–3 215
- Info–4 Additional Information 216
- Note to Table: 217
- Info–6 Additional Information 218
- Typographic Conventions 218
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