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- Inhaltsverzeichnis
- LESEZEICHEN
- User Guide 1
- RapidIO II MegaCore Function 1
- Contents 3
- Contents v 5
- Chapter 5. Signals 6
- Chapter 6. Software Interface 6
- Chapter 7. Testbench 6
- 1. About The RapidIO II 9
- MegaCore Function 9
- Releases 10
- RapidIO II IP Core Features 10
- Features 11
- Device Family Support 12
- IP Core Verification 13
- Hardware Testing 14
- Interoperability Testing 14
- Note to Table 1–3: 16
- Notes to Table 1–4: 16
- Installation and Licensing 17
- 2. Getting Started 19
- Simulating IP Cores 22
- Transceiver Settings 26
- External Transceiver PLL 26
- 3. Parameter Settings 31
- Note to Table 3–1: 32
- Enable 16-Bit Device ID Width 33
- Logical Layer Settings 34
- Capability Registers Settings 35
- Device ID 36
- Vendor ID 36
- Revision ID 36
- Assembly ID 36
- Assembly Information CAR 37
- Enable Flow Control Support 38
- Enable Switch Support 38
- Number of Ports 38
- Port Number 39
- Maximum PDU 39
- Destination Operations CAR 40
- Port General Control CSR 40
- Port 0 Control CSR 41
- Lane n Status 0 CSR 41
- Extended Features Pointer CSR 41
- 4. Functional Description 43
- Note to Table 4–2: 44
- Clocking and Reset Structure 45
- Notes to Table 4–3: 46
- RapidIO II 47
- Transactions 55
- Notes to Table 4–6: 57
- Notes to Table 4–7: 59
- Note to Table 4–8: 59
- Note to Figure 4–9: 66
- Note to Table 4–10: 70
- Notes to Table 4–11: 71
- Table 6–60 on page 6–40 72
- Note to Table 4–12: 73
- Maintenance Module 74
- Maintenance Interface Signals 75
- Doorbell Module Block Diagram 86
- Preserving Transaction Order 87
- Doorbell Module Signals 88
- Generating a Doorbell Message 88
- Receiving a Doorbell Message 89
- Transaction ID Ranges 90
- Notes to Table 4–24: 92
- Note to Table 4–26: 94
- Note to Table 4–27: 95
- field 97
- User Receiving Write Request 100
- Logical Layer Interfaces 101
- Transport Layer 112
- Receiver 113
- Transmitter 114
- Physical Layer 115
- Physical Layer Interfaces 116
- Low-level Interface Receiver 116
- CRC Checking and Removal 117
- Protocol Violations 119
- Fatal Errors 119
- Maintenance Avalon-MM Slave 120
- Maintenance Avalon-MM Master 121
- Port-Write Reception Module 122
- Input/Output Avalon-MM Slave 122
- Input/Output Avalon-MM Master 123
- 5. Signals 125
- Physical Layer Signals 126
- Low Latency Signals 127
- Multicast Event Signals 128
- Chapter 5: Signals 5–5 129
- Note to Table 5–7: 130
- Chapter 5: Signals 5–7 131
- 5–8 Chapter 5: Signals 132
- Register-Related Signals 133
- Avalon-MM Interface Signals 133
- Note to Table 5–12: 134
- Chapter 5: Signals 5–11 135
- Note to Table 5–15: 136
- Error Reporting Signals 137
- 5–14 Chapter 5: Signals 138
- 6. Software Interface 139
- Memory Map 140
- Physical Layer Registers 144
- Note to Table 6–9: 147
- Note to Table 6–14: 154
- Note to Table 6–15: 158
- Note to Table 6–17: 160
- Note to Table 6–22: 164
- Note to Table 6–23: 164
- Note to Table 6–24: 165
- Note to Table 6–25: 165
- Note to Table 6–26: 166
- Note to Table 6–27: 167
- Notes to Table 6–28: 168
- Notes to Table 6–29: 169
- Note to Table 6–30: 169
- Note to Table 6–31: 169
- Notes to Table 6–32: 170
- Note to Table 6–34: 171
- Note to Table 6–35: 171
- Note to Table 6–36: 172
- Note to Table 6–37: 172
- Transmit Port-Write Registers 174
- Receive Port-Write Registers 175
- Note to Table 6–59: 178
- Error Management Registers 180
- Note to Table 6–66: 181
- Notes to Table 6–67: 183
- Notes to Table 6–70: 185
- Notes to Table 6–71: 185
- Doorbell Message Registers 191
- Note to Table 6–89: 193
- 7. Testbench 195
- 7–2 Chapter 7: Testbench 196
- Testbench Overview 196
- Testbench Sequence 197
- 7–4 Chapter 7: Testbench 198
- Chapter 7: Testbench 7–5 199
- SWRITE Transactions 200
- NREAD Transactions 200
- NWRITE_R Transactions 201
- NWRITE Transactions 202
- Doorbell Transactions 202
- Port-Write Transactions 203
- Testbench Completion 204
- Chapter 7: Testbench 7–11 205
- 7–12 Chapter 7: Testbench 206
- A. Initialization Sequence 207
- MegaCore Function v12.1 209
- Additional Information 213
- Info–2 Additional Information 214
- Document Revision History 214
- Additional Information Info–3 215
- Info–4 Additional Information 216
- Note to Table: 217
- Info–6 Additional Information 218
- Typographic Conventions 218
Inhaltsverzeichnis
101 Innovation DriveSan Jose, CA 95134www.altera.com UG-01116-2.1 User GuideRapidIO II MegaCore FunctionDocument last updated for Altera Complete Desi
1–2 Chapter 1: About The RapidIO II MegaCore FunctionFeaturesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideNew Features in the
4–58 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideThe initial ten byt
Chapter 4: Functional Description 4–59Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideFigure 4–22 shows t
4–60 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideUser Sending Read R
Chapter 4: Functional Description 4–61Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideFigure 4–23 shows t
4–62 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideThe initial 12 byte
Chapter 4: Functional Description 4–63Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTable 4–38 lists th
4–64 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideFigure 4–24 shows t
Chapter 4: Functional Description 4–65Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideNREAD Response Tran
4–66 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideThe initial eight b
Chapter 4: Functional Description 4–67Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideFigure 4–25 shows t
Chapter 1: About The RapidIO II MegaCore Function 1–3FeaturesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide Physical layer fea
4–68 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideThe initial eight b
Chapter 4: Functional Description 4–69Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideFigure 4–26 shows t
4–70 Chapter 4: Functional DescriptionTransport LayerRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideTransport Layer The Transpor
Chapter 4: Functional Description 4–71Transport LayerAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideThe Transport layer module i
4–72 Chapter 4: Functional DescriptionTransport LayerRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide Routes packets with a tt v
Chapter 4: Functional Description 4–73Physical LayerAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideThe Transport layer polls the
4–74 Chapter 4: Functional DescriptionPhysical LayerRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide FIFO buffer with level outp
Chapter 4: Functional Description 4–75Physical LayerAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideCRC Checking and RemovalThe P
4–76 Chapter 4: Functional DescriptionError Detection and ManagementRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideTo meet the R
Chapter 4: Functional Description 4–77Error Detection and ManagementAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideThe RapidIO I
1–4 Chapter 1: About The RapidIO II MegaCore FunctionDevice Family SupportRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide Input
4–78 Chapter 4: Functional DescriptionError Detection and ManagementRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide Malformed r
Chapter 4: Functional Description 4–79Error Detection and ManagementAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide Illegal Tra
4–80 Chapter 4: Functional DescriptionError Detection and ManagementRapidIO II MegaCore Function August 2014 Altera CorporationUser GuidePort-Write Re
Chapter 4: Functional Description 4–81Error Detection and ManagementAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide Illegal Tra
4–82 Chapter 4: Functional DescriptionError Detection and ManagementRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide Unsupported
August 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide5. SignalsThis chapter lists the RapidIO II IP core signals. Signals are listed w
5–2 Chapter 5: SignalsPhysical Layer SignalsRapidIO II MegaCore Function August 2014 Altera CorporationUser GuidePhysical Layer SignalsTable 5–3 throu
Chapter 5: Signals 5–3Physical Layer SignalsAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideStatus Packet and Error Monitoring Si
5–4 Chapter 5: SignalsPhysical Layer SignalsRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideMulticast Event SignalsTable 5–5 list
Chapter 5: Signals 5–5Physical Layer SignalsAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTable 5–8 lists the Arria 10 Native P
Chapter 1: About The RapidIO II MegaCore Function 1–5IP Core VerificationAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTable 1–
5–6 Chapter 5: SignalsPhysical Layer SignalsRapidIO II MegaCore Function August 2014 Altera CorporationUser Guiderx_signaldetect[n:0]OutputIndicates t
Chapter 5: Signals 5–7Physical Layer SignalsAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guidereconfig_address_ch1[9:0]InputArria 1
5–8 Chapter 5: SignalsPhysical Layer SignalsRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideTo control the transceivers, you must
Chapter 5: Signals 5–9Logical and Transport Layer SignalsAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideRegister-Related Signals
5–10 Chapter 5: SignalsLogical and Transport Layer SignalsRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideAvalon-ST Pass-Through
Chapter 5: Signals 5–11Error Management Extension SignalsAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuidePacket and Error Monitor
5–12 Chapter 5: SignalsError Management Extension SignalsRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideTable 5–15. Capture Sign
Chapter 5: Signals 5–13Error Management Extension SignalsAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideError Reporting Signals
5–14 Chapter 5: SignalsError Management Extension SignalsRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide
August 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide6. Software InterfaceThe RapidIO IP core supports the following sets of registers
1–6 Chapter 1: About The RapidIO II MegaCore FunctionIP Core VerificationRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideConstrai
6–2 Chapter 6: Software InterfaceMemory MapRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideMemory MapTable 6–2 lists the RapidIO
Chapter 6: Software Interface 6–3Memory MapAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTable 6–3 lists the CARs and CSRs. Tab
6–4 Chapter 6: Software InterfaceMemory MapRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide0x4CProcessing Element Logical Layer C
Chapter 6: Software Interface 6–5Memory MapAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideExtended Features Space: Error Managem
6–6 Chapter 6: Software InterfacePhysical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuidePhysical Layer Registers
Chapter 6: Software Interface 6–7Physical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide The LP-Serial Lane Ext
6–8 Chapter 6: Software InterfacePhysical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideTable 6–7. Port Link Tim
Chapter 6: Software Interface 6–9Physical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideDISCOVER[29] RWThis devi
6–10 Chapter 6: Software InterfacePhysical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideTable 6–12. Port 0 Loca
Chapter 6: Software Interface 6–11Physical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide1.25_GB_ENABLE[24] RWIn
Chapter 1: About The RapidIO II MegaCore Function 1–7Performance and Resource UtilizationAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUs
6–12 Chapter 6: Software InterfacePhysical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideINACTIVE_LNS_EN [3] ROI
Chapter 6: Software Interface 6–13Physical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideIDLE_SEQUENCE[29] ROInd
6–14 Chapter 6: Software InterfacePhysical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideOUT_ERR_STOP[16] ROIndi
Chapter 6: Software Interface 6–15Physical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideIN_ERR_STOP[8] ROInput
6–16 Chapter 6: Software InterfacePhysical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuidePORT_ERR[2] RW1CThis bi
Chapter 6: Software Interface 6–17Physical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTable 6–15. Port 0 Cont
6–18 Chapter 6: Software InterfacePhysical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuidePORT_DIS[23] RWPort dis
Chapter 6: Software Interface 6–19Physical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideEXTENDED_PWIDTH_OVRIDE[
6–20 Chapter 6: Software InterfacePhysical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideSTOP_ON_PRT_FAIL_ENCOUN
Chapter 6: Software Interface 6–21Physical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTable 6–16. LP-Serial L
1–8 Chapter 1: About The RapidIO II MegaCore FunctionDevice Speed GradesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideDevice Sp
6–22 Chapter 6: Software InterfacePhysical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideReceiver Trained[14] RO
Chapter 6: Software Interface 6–23Physical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTable 6–18. LP-Serial L
6–24 Chapter 6: Software InterfacePhysical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideConnected port transmit
Chapter 6: Software Interface 6–25Physical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTable 6–21. LP-Serial L
6–26 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideThe RapidI
Chapter 6: Software Interface 6–27Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTable 6–24
6–28 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideExtended r
Chapter 6: Software Interface 6–29Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTable 6–27
6–30 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideImplementa
Chapter 6: Software Interface 6–31Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide Implemen
Chapter 1: About The RapidIO II MegaCore Function 1–9Installation and LicensingAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideAl
6–32 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideCommand an
Chapter 6: Software Interface 6–33Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide Table 6–
6–34 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideMaintenanc
Chapter 6: Software Interface 6–35Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTransmit M
6–36 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideTransmit P
Chapter 6: Software Interface 6–37Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideReceive Po
6–38 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideRefer to “
Chapter 6: Software Interface 6–39Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideInput/Outp
6–40 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideInput/Outp
Chapter 6: Software Interface 6–41Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideInput/Outp
1–10 Chapter 1: About The RapidIO II MegaCore FunctionInstallation and LicensingRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideO
6–42 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideError Mana
Chapter 6: Software Interface 6–43Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide 0x31CLogi
6–44 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideILL_TRAN_T
Chapter 6: Software Interface 6–45Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide Implement
6–46 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideUNSUPPORT_
Chapter 6: Software Interface 6–47Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTable 6–69
6–48 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuidedeviceID[2
Chapter 6: Software Interface 6–49Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideLoss of de
6–50 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideReceived c
Chapter 6: Software Interface 6–51Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTable 6–76
August 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide2. Getting StartedYou can customize the RapidIO II IP core to support a wide vari
6–52 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideTable 6–79
Chapter 6: Software Interface 6–53Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideDoorbell M
6–54 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideTable 6–85
Chapter 6: Software Interface 6–55Transport and Logical Layer RegistersAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideINFORMATIO
6–56 Chapter 6: Software InterfaceTransport and Logical Layer RegistersRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideTX_CPL[1]
August 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide7. TestbenchThe RapidIO II IP core includes a demonstration testbench for your us
7–2 Chapter 7: TestbenchTestbench OverviewRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide NWRITE_R NWRITE NREAD DOORBELL message
Chapter 7: Testbench 7–3Testbench SequenceAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideFigure 7–1 illustrates the system speci
7–4 Chapter 7: TestbenchTestbench SequenceRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideNext, basic programming of the internal
Chapter 7: Testbench 7–5Testbench SequenceAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideMaintenance Write and Read Transactions
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logosare trademar
2–2 Chapter 2: Getting StartedIFiles Generated for Altera IP Cores (Legacy Parameter Editor)RapidIO II MegaCore Function August 2014 Altera Corporatio
7–6 Chapter 7: TestbenchTestbench SequenceRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideSWRITE TransactionsThe next set of oper
Chapter 7: Testbench 7–7Testbench SequenceAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideThe NREAD request packets are received
7–8 Chapter 7: TestbenchTestbench SequenceRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideNWRITE Transactions To perform NWRITE o
Chapter 7: Testbench 7–9Testbench SequenceAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideNext, the test pushes five DOORBELL mes
7–10 Chapter 7: TestbenchTestbench CompletionRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideThe testbench performs this test fiv
Chapter 7: Testbench 7–11Transceiver Level Connections in the TestbenchAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTransceive
7–12 Chapter 7: TestbenchTransceiver Level Connections in the TestbenchRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide
August 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideA. Initialization SequenceThis appendix describes the most basic initialization s
A–2 Appendix A: Initialization SequenceRapidIO II MegaCore Function August 2014 Altera CorporationUser Guidef For more information about initializing
August 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideB. Differences Between RapidIO IIMegaCore Function v12.1 and RapidIOMegaCore Func
Chapter 2: Getting Started 2–3IFiles Generated for Altera IP Cores by Qsys (Legacy Parameter Editor)August 2014 Altera Corporation RapidIO II MegaCore
B–2 Appendix B: Differences Between RapidIO II MegaCore Function v12.1 and RapidIO MegaCore Function v12.1RapidIO II MegaCore Function August 2014 Alt
Appendix B: Differences Between RapidIO II MegaCore Function v12.1 and RapidIO MegaCore Function v12.1 B–3August 2014 Altera Corporation RapidIO II Me
B–4 Appendix B: Differences Between RapidIO II MegaCore Function v12.1 and RapidIO MegaCore Function v12.1RapidIO II MegaCore Function August 2014 Alt
August 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideAdditional InformationThis chapter provides additional information about the docu
Info–2 Additional InformationDocument Revision HistoryRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideJune 2014Continued on next
Additional Information Info–3Document Revision HistoryAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideJune 2014, continuedContinu
Info–4 Additional InformationDocument Revision HistoryRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideJune 2014, continuedContinu
Additional Information Info–5How to Contact AlteraAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideHow to Contact AlteraTo locate
Info–6 Additional InformationTypographic ConventionsRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideInitial Capital LettersIndica
2–4 Chapter 2: Getting StartedFiles Generated for Altera IP CoresRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideFiles Generated
Chapter 2: Getting Started 2–5Simulating IP CoresAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideYou can use the functional simul
2–6 Chapter 2: Getting StartedIntegrating Your IP Core in Your DesignRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideSimulating t
Chapter 2: Getting Started 2–7Integrating Your IP Core in Your DesignAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideAltera recom
2–8 Chapter 2: Getting StartedIntegrating Your IP Core in Your DesignRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideTransceiver
Chapter 2: Getting Started 2–9Compiling the Full Design and Programming the FPGAAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideW
2–10 Chapter 2: Getting StartedInstantiating Multiple RapidIO II IP CoresRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideInstanti
Chapter 2: Getting Started 2–11Instantiating Multiple RapidIO II IP CoresAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideFigure 2
August 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideContentsChapter 1. About The RapidIO II MegaCore FunctionFeatures . . . . . . . .
2–12 Chapter 2: Getting StartedInstantiating Multiple RapidIO II IP CoresRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide
August 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide3. Parameter SettingsYou customize the RapidIO II IP core by specifying parameter
3–2 Chapter 3: Parameter SettingsPhysical Layer SettingsRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideSupported ModesThe Suppor
Chapter 3: Parameter Settings 3–3Transport Layer SettingsAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTransport Layer Settings
3–4 Chapter 3: Parameter SettingsLogical Layer SettingsRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideDisable Destination ID Che
Chapter 3: Parameter Settings 3–5Capability Registers SettingsAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideIf the Doorbell mod
3–6 Chapter 3: Parameter SettingsCapability Registers SettingsRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide1 The settings on t
Chapter 3: Parameter Settings 3–7Capability Registers SettingsAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideAssembly Vendor IDA
3–8 Chapter 3: Parameter SettingsCapability Registers SettingsRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideEnable Standard Rou
Chapter 3: Parameter Settings 3–9Capability Registers SettingsAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuidePort Number Port nu
iv ContentsRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideI/O Master Configuration . . . . . . . . . . . . . . . . . . . . . . .
3–10 Chapter 3: Parameter SettingsCommand and Status Registers SettingsRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideDestinatio
Chapter 3: Parameter Settings 3–11Command and Status Registers SettingsAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideHost Reset
3–12 Chapter 3: Parameter SettingsError Management Registers SettingsRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide If you do
August 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide4. Functional DescriptionInterfacesThe Altera RapidIO II IP core supports the fol
4–2 Chapter 4: Functional DescriptionInterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideIn variations of the RapidIO II IP
Chapter 4: Functional Description 4–3Clocking and Reset StructureAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guidef More detailed
4–4 Chapter 4: Functional DescriptionClocking and Reset StructureRapidIO II MegaCore Function August 2014 Altera CorporationUser Guidef For more infor
Chapter 4: Functional Description 4–5Clocking and Reset StructureAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide rx_ready, rx_an
4–6 Chapter 4: Functional DescriptionClocking and Reset StructureRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideThe assertion of
Chapter 4: Functional Description 4–7Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideLogical Layer Interf
Contents vAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideAvalon-MM Interface Byte Ordering . . . . . . . . . . . . . . . . . .
4–8 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide1 The Doorbell Logic
Chapter 4: Functional Description 4–9Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideThe interface suppor
4–10 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideInput/Output Avalon
Chapter 4: Functional Description 4–11Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideThe I/O Avalon-MM M
4–12 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser Guidewhere: rio_addr[33:
Chapter 4: Functional Description 4–13Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideFigure 4–5 shows a
4–14 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideFor information abo
Chapter 4: Functional Description 4–15Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTable 4–7 lists the
4–16 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide000100 1 0000_0000_
Chapter 4: Functional Description 4–17Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTable 4–8 lists the
vi ContentsRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideLogical Layer Error Management . . . . . . . . . . . . . . . . . . .
4–18 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideThe RapidIO II IP c
Chapter 4: Functional Description 4–19Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideInput/Output Avalon
4–20 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideInput/Output Avalon
Chapter 4: Functional Description 4–21Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideIP Core ActionsIn r
4–22 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideThe RapidIO II IP c
Chapter 4: Functional Description 4–23Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideYou can change the
4–24 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide Increments the CO
Chapter 4: Functional Description 4–25Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideInput/Output Slave
4–26 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideFigure 4–11 shows a
Chapter 4: Functional Description 4–27Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTranslation Window
Contents viiAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideDoorbell Transactions . . . . . . . . . . . . . . . . . . . . . . .
4–28 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide1 0000_0000_0001_00
Chapter 4: Functional Description 4–29Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideIn read requests, i
4–30 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideAvalon-MM value com
Chapter 4: Functional Description 4–31Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideInput/Output Avalon
4–32 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideMaintenance ModuleT
Chapter 4: Functional Description 4–33Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideMaintenance Interfa
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4–36 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser Guide For a MAINTENANCE
Chapter 4: Functional Description 4–37Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuidePort-Write Transmis
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Chapter 4: Functional Description 4–39Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guidewrite transaction.
4–40 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideUser Receiving MAIN
Chapter 4: Functional Description 4–41Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideUser Sending MAINTE
4–42 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideUser Receiving MAIN
Chapter 4: Functional Description 4–43Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideThe RapidIO II IP c
4–44 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideDoorbell ModuleThe
Chapter 4: Functional Description 4–45Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide Error Management
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Chapter 4: Functional Description 4–47Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideThe corresponding i
August 2014 Altera Corporation RapidIO II MegaCore FunctionUser Guide1. About The RapidIO IIMegaCore FunctionThe RapidIO interconnect—an open standard
4–48 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideAvalon-ST Pass-Thro
Chapter 4: Functional Description 4–49Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideIf the Input-Output
4–50 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuideTable 4–25 and Tabl
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Chapter 4: Functional Description 4–53Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuidePass-Through Interf
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Chapter 4: Functional Description 4–55Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTable 4–30 lists th
4–56 Chapter 4: Functional DescriptionLogical Layer InterfacesRapidIO II MegaCore Function August 2014 Altera CorporationUser GuidePass-Through Interf
Chapter 4: Functional Description 4–57Logical Layer InterfacesAugust 2014 Altera Corporation RapidIO II MegaCore FunctionUser GuideTable 4–32 lists th
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