Altera Stratix V Avalon-ST Bedienungsanleitung

Stratix V Avalon-ST Interface for PCIe SolutionsUser GuideLast updated for Altera Complete Design Suite: 14.1SubscribeSend FeedbackUG-01097_avst2014.1

Figure 1-4: Example Design Preset ParametersIn this example design, the following parameters must be set to match the values set in the DUT:• Targeted

Signal Name Direction Descriptiontxfc_maxOutput When asserted, indicates that Transaction Layer has enoughcredits to send maximum payload TLPs of all

Signal Name Direction Descriptionerr_tlmalfOutput When asserted, indicates a malformed TLP was detected anddropped. This is a real-time active high pu

Parity SignalsYou enable parity checking by selecting Enable byte parity ports on the Avalon-ST interface under theSystem Settings heading of the para

Signal Name Direction Descriptioncfg_par_errOutput When asserted for a single cycle, indicates that a parity error wasdetected in a TLP that was route

Note: You can also use the Configuration Space signals to read Configuration Space registers. For moreinformation, refer to Transaction Layer Configur

Figure 5-37: LMI WriteOnly writeable configuration bits are overwritten by this operation. Read-only bits are not affected. LMIwrite operations are no

Signal Direction DescriptionInput • [0]: Attention button pressed. This signal should be assertedwhen the attention button is pressed. If no attention

tl_cfg_sts Configuration Space Register Description[46:31] Link Status Register[15:0] Records the following link status informa‐tion:• Bit 15: link au

Configuration Space Register Access TimingFigure 5-38: tl_cfg_ctl TimingThe following figure shows typical traffic on the tl_cfg_ctl bus. The tl_cfg_a

Figure 5-39: Multiplexed Configuration Register Information Available on tl_cfg_ctlFields in blue are available only for Root Ports.01cfg_dev_ctrl[15:

Debug FeaturesDebug features allow observation and control of the Hard IP for faster debugging of system-levelproblems.Related InformationDebugging on

Register Width Direction Descriptioncfg_link_ctrl16 Output cfg_link_ctrl[15:0]is the primary Link Controlof the PCI Express capability structure.For G

Register Width Direction Descriptioncfg_msi_addr64 Output cfg_msi_add[63:32] is the message signaledinterrupt (MSI) upper message address. cfg_msi_add

Register Width Direction Descriptioncfg_tcvcmap24 Output Configuration traffic class (TC)/virtual channel(VC) mapping. The Application Layer uses this

Bit(s) Field Description[6:4] multiple messageenableThis field indicates permitted values for MSI signals. For example,if “100” is written to this fie

Table 5-20: Hard IP Reconfiguration SignalsSignal Direction Descriptionhip_reconfig_clkInput Reconfiguration clock. The frequency range for this clock

Figure 5-41: Hard IP Reconfiguration Bus Timing of Read-Only Registersavmm_clkhip_reconfig_rst_nuser_modeser_shift_loadinterface_selavmm_wravmm_wrdata

Signal Direction Descriptionpme_to_srOutput Power management turn off status register.Root Port—This signal is asserted for 1 clock cycle when the Roo

Figure 5-42: Layout of Power Management Capabilities Registerdata_selectdata_scale PM_statePME_ENPME_status reserved15 011623 8 2791213142431reservedd

Figure 5-43: pme_to_sr and pme_to_cr in an Endpoint IP coreThe following figure illustrates the behavior of pme_to_sr and pme_to_cr in an Endpoint. Fi

Variant Logical InterfacesGen1 and Gen2 ×2 3Gen1 and Gen2 ×4 5Gen1 and Gen2 ×8 10Gen3 ×1 3Gen3 ×2 4Gen3 ×4 6Gen3 ×8 11For more information about the T

Recommended Speed GradesTable 1-5: Stratix V Recommended Speed Grades for All Link Widths and Application Layer ClockFrequenciesAltera recommends sett

Physical Layout of Hard IP in Stratix V GX/GT/GS DevicesStratix V devices include one, two, or four Hard IP for PCI Express IP cores. The following fi

Channel Placement in Arria V GZ and Stratix V GX/GT/GS DevicesFigure 5-45: Arria V GZ and Stratix V GX/GT/GS Gen1 and Gen2 Channel Placement Using the

Figure 5-46: Arria V GZ and Stratix V GX/GT/GS Gen3 Channel Placement Using the CMU and ATX PLLsGen3 requires two PLLs to facilitate rate switching be

Figure 5-47: Arria V GZ and Stratix V GX/GT/GS Gen1 and Gen2 Channel Placement Using the ATX PLLSelecting the ATX PLL has the following advantages ove

Table 5-26: PIPE Interface SignalsSignal Direction Descriptiontxdata0[7:0]Output Transmit data <n>. This bus transmits data on lane <n>.tx

Signal Direction Descriptionpowerdown0[1:0] Output Power down <n>. This signal requests the PHY to change itspower state to the specified state

Signal Direction Descriptionsim_pipe_rate[1:0]Output The 2-bit encodings have the following meanings:• 2’b00: Gen1 rate (2.5 Gbps)• 2’b01: Gen2 rate (

Signal Direction Description• 5’b11010: Speed.Recovery• 5’b11011: Recovery.Equalization, Phase 0• 5’b11100: Recovery.Equalization, Phase 1• 5’b11101:

Test SignalsTable 5-27: Test Interface SignalsThe test_in bus provides run-time control and monitoring of the internal state of the IP core.Signal Dir

Registers62014.08.18UG-01097_avstSubscribeSend FeedbackCorrespondence between Configuration Space Registers and the PCIeSpecificationTable 6-1: Corres

Link Rate Link Width InterfaceWidthApplication ClockFrequency (MHz)Recommended Speed GradesGen3x1 64 bits 125 –1, –2, –3, –4x2 64 bits 250 –1, –2, –3,

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x170:0x17C Reserved N/A0x180:0x1FC Virtual channel arbit

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x018 Base Address 2Secondary Latency Timer, Subordinate

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x058 Message Upper Address MSI and MSI-X Capability Stru

Type 0 Configuration Space RegistersFigure 6-1: Type 0 Configuration Space Registers - Byte Address Offsets and LayoutEndpoints store configuration da

Type 1 Configuration Space RegistersFigure 6-2: Type 1 Configuration Space Registers (Root Ports)0x00000x004Device ID31242316158700x0080x00C0x0100x014

Figure 6-4: MSI-X Capability Structure0x0680x06C0x070Message Control Next Cap PtrMSI-X Table OffsetMSI-X Pending Bit Array (PBA) Offset31 24 23 16 15

Figure 6-7: PCI Express Capability Structure - Byte Address Offsets and LayoutIn the following table showing the PCI Express Capability Structure, reg

Altera-Defined VSEC RegistersFigure 6-8: VSEC RegistersThis extended capability structure supports Configuration via Protocol (CvP) programming and de

Table 6-3: Altera‑Defined Vendor Specific HeaderYou can specify these values when you instantiate the Hard IP. These registers are read-only at run-ti

Table 6-7: CvP StatusThe CvP Status register allows software to monitor the CvP status signals.Bits Register Description Reset Value Access[31:26] Res

Related Information• Parameter Settings on page 4-1• Getting Started with the Stratix V Hard IP for PCI Express on page 2-1• All Development KitsUG-01

Bits Register Description Reset Value Access[1] HIP_CLK_SEL. Selects between PMA and fabric clock when USER_MODE = 1 and PLD_CORE_READY = 1. The follo

Bits Register Description Reset Value Access[1] START_XFER. Sets the CvP output to the FPGA control blockindicating the start of a transfer.1’b0 RW[0]

Bits Register Description Reset Value Access[0] Mask for the RX buffer uncorrectable ECC error. 1b’1 RWSUncorrectable Internal Error Status RegisterTa

Bits Register DescriptionResetValueAccess[1] When set, indicates a retry buffer uncorrectable ECC error.0RW1CS[0] When set, indicates a RX buffer unco

Bits Register Description Reset Value Access[5] When set, indicates a configuration error has been detected inCvP mode which is reported as correctabl

Reset and Clocks72014.12.15UG-01097_avstSubscribeSend FeedbackStratix V Hard IP for PCI Express IP Core includes both a soft reset controller and a ha

Figure 7-1: Reset Controller Block DiagramExample Designaltpcie_dev_hip_<if>_hwtcl.valtpcied_<dev>_hwtcl.svTransceiver HardReset Logic/Sof

Reset Sequence for Hard IP for PCI Express IP Core and Application LayerFigure 7-2: Hard IP for PCI Express and Application Logic Reset SequenceYour A

Figure 7-3: RX Transceiver Reset Sequencebusy_xcvr_reconfigrx_pll_lockedrx_analogresetltssmstate[4:0]txdetectrx_loopbackpipe_phystatuspipe_rxstatus[2:

For descriptions of the available reset signals, refer to Reset Signals, Status, and Link Training Signals.Related InformationReset, Status, and Link

Getting Started with the Stratix V Hard IP forPCI Express22014.12.15UG-01097_avstSubscribeSend FeedbackThis section provides instructions to help you

As this figure indicates, the IP core includes the following clock domains:pclkThe transceiver derives pclk from the 100 MHz refclk signal that you mu

Link Width Maximum Link Rate Avalon Interface Width coreclkout_hip×8 Gen1 64 250 MHz×8 Gen1128125 MHz×1Gen2 64125 MHz×2Gen2 64125 MHz×4 Gen2 64 250 MH

Clock SummaryTable 7-4: Clock SummaryName Frequency Clock Domaincoreclkout_hip62.5, 125 or 250 MHz Avalon-ST interface between the Transaction andAppl

Interrupts82014.08.18UG-01097_avstSubscribeSend FeedbackInterrupts for EndpointsThe Stratix V Hard IP for PCI Express provides support for PCI Express

Figure 8-1: MSI Handler BlockMSI HandlerBlockapp_msi_reqapp_msi_ackapp_msi_tc[2:0]app_msi_num[4:0]pex_msi_numapp_int_stscfg_msicsr[15:0]The following

Figure 8-3: MSI Request ExampleEndpoint8 Requested2 AllocatedRoot ComplexCPUInterrupt RegisterRootPortInterruptBlockThe following table describes thre

Figure 8-4: MSI Interrupt Signals Timingclkapp_msi_reqapp_msi_tc[2:0]app_msi_num[4:0]app_msi_ack1 2 3 5 647validvalidRelated InformationCorrespondence

Figure 8-5: MSI-X Interrupt ComponentsHostRXTXRXTXMSI-XPCIe with Avalon-ST I/FMSI-X TableIRQProcessorMSI-X PBAIRQ SourceApplication LayerHost SW Prog

Figure 8-7: MSI-X PBA TablePending Bits 0 through 63Pending Bits 64 through 127Pending Bits ((N - 1) div 64) × 64 through N - 1QWORD 0QWORD 1QWORD ((

Figure 8-9: Legacy Interrupt Deassertionclkapp_int_stsapp_int_ackRelated InformationCorrespondence between Configuration Space Registers and the PCIe

scripts to compile and simulate the Stratix V Hard IP for PCI Express IP Core. This example designprovides a simple method to perform basic testing of

Error Handling92014.12.15UG-01097_avstSubscribeSend FeedbackEach PCI Express compliant device must implement a basic level of error management and can

Physical Layer ErrorsTable 9-2: Errors Detected by the Physical LayerThe following table describes errors detected by the Physical Layer. Physical Lay

Transaction Layer ErrorsTable 9-4: Errors Detected by the Transaction LayerError Type DescriptionPoisoned TLP received Uncorrectable(non-fatal)This er

Error Type DescriptionIn all cases the TLP is deleted in the Hard IP block andnot presented to the Application Layer. If the TLP is anon-posted reques

Error Type DescriptionUnexpected completion Uncorrectable(non-fatal)This error is caused by an unexpected completiontransaction. The Hard IP block han

Error Type DescriptionMalformed TLP Uncorrectable(fatal)This error is caused by any of the following conditions:• The data payload of a received TLP e

Poisoned TLPs can also set the parity error bits in the PCI Configuration Space Status register.Table 9-5: Parity Error ConditionsStatus Bit Condition

Figure 9-2: Correctable Error Status RegisterThe default value of all the bits of this register is 0. An error status bit that is set indicates that t

IP Core Architecture102014.08.18UG-01097_avstSubscribeSend FeedbackThe Stratix V Hard IP for PCI Express implements the complete PCI Express protocol

Figure 10-1: Stratix V Hard IP for PCI Express Using the Avalon-ST InterfaceClockDomainCrossing(CDC)Data LinkLayer(DLL)Transaction Layer (TL)PHYMAC Ha

Figure 2-2: Complete Gen1 ×8 Endpoint (DUT) Connected to Example Design (APPS)The example design includes the following components:• DUT—This is Gen1

The following interfaces provide access to the Application Layer’s Configuration Space Registers:• The LMI interface• The Avalon-MM PCIe reconfigurati

Clocks and ResetThe PCI Express Base Specification requires an input reference clock, which is called refclk in this design.The PCI Express Base Speci

Related Information• Interrupts for Endpoints on page 5-39• Interrupts for Root Ports on page 5-40PIPEThe PIPE interface implements the Intel-designed

Figure 10-2: Architecture of the Transaction Layer: Dedicated Receive BufferTransaction Layer TX DatapathTransaction Layer RX DatapathAvalon-STRX Cont

The Configuration Space also generates all messages (PME#, INT, error, slot power limit), MSI requests,and completion packets from configuration reque

Figure 10-3: Configuration Space Bypass ModeCustomConfiguration SpaceRX Buffer &Flow ControlConfigurationSpace(Disabled)Avalon-ST RXTransaction La

Note: Altera does not support the use of the LMI interface to read and write the other registers infunction0 of the Hard IP for PCI Express Configurat

The following list summarizes the behavior of the Transaction Layer error handling in ConfigurationSpace Bypass Mode:• The Translation Layer discards

• Real-time error signals are routed to the Application Layer using the error status output signals listedin the “Configuration Space Bypass Mode Outp

Protocol Extensions SupportedThe Transaction Layer supports the following protocol extensions:• TLP Processing Hints (TPH)—Supports both a Requester a

Table 2-1: Parameters to Specify on the Generation Tab in QsysParameter ValueTestbench SystemCreate testbench Qsys system Standard, BFMs for standard

Figure 10-5: Data Link LayerTo Transaction LayerTx Transaction LayerPacket Description & DataTransaction LayerPacket GeneratorRetry BufferTo Physi

• ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and generates the sequencenumber of transmitted packets.• Transaction Layer Packet Checker—T

Figure 10-6: Physical Layer ArchitectureScrambler8B10BEncoderLane nTX+ / TX-Scrambler8B10BEncoderLane 0TX+ / TX-Descrambler8B10BDecoderLane nRX+ / RX-

The PHYMAC block comprises four main sub-blocks:• MAC Lane—Both the RX and the TX path use this block.• On the RX side, the block decodes the Physical

Transaction Layer Protocol (TLP) Details112014.08.18UG-01097_avstSubscribeSend FeedbackSupported Message TypesINTX MessagesThe following table describ

MessageRootPortEndpointGenerated byCommentsAppLayerCore Core(withAppLayerinput)Deassert_INTBReceive Transmit No No NoDeassert_INTCReceive Transmit No

Error Signaling MessagesTable 11-3: Error Signaling MessagesMessageRootPortEndpointGenerated byCommentsAppLayerCore Core (withApp Layerinput)ERR_CORRX

Locked Transaction MessageTable 11-4: Locked Transaction MessageMessage Root Port EndpointGenerated byCommentsAppLayerCore Core (withApp Layerinput)Un

Message Root Port EndpointGenerated byCommentsAppLayerCore Core (withApp Layerinput)VendorDefinedType 1TransmitReceiveTransmitReceiveYes No NoHot Plug

Message Root Port EndpointGenerated byCommentsAppLayerCore Core (withApp Layerinput)AttentionButton_Pressed(Endpoint only)Receive Transmit No No YesN/

You can leave the default settings for all other items.3. Click Generate to generate files for Quartus II synthesis.4. Click Finish when the generatio

• The Type 0 Configuration TLPs are only routed to the Configuration Space of the Hard IP and are notsent downstream on the PCI Express link.• The Typ

• A Memory Write or Message Request with the Relaxed Ordering Attribute bit clear (b’0) must not passany other Memory Write or Message Request.• A Mem

Can the Row Passthe Column?Posted Req Non Posted ReqCompletionMemory Write orMessage ReqRead Request I/O or Cfg Write ReqCmplCmpl NoY/NNoNoYes Yes Yes

Figure 11-1: Design Including Legacy PCI Buses Requiring Strong OrderingProducerPCI-toPCI BridgePCI BusFlagPostedWrite BufferConsumerPCI BusMemoryRead

Figure 11-2: PCI Express Design Using Relaxed OrderingRootComplexPCIeEndpointSwitchWrite BufferFullCPUMemoryPCIe Bridge to PCI or PCI-XLegacyEndpointP

Throughput Optimization122014.12.15UG-01097_avstSubscribeSend FeedbackThe PCI Express Base Specification defines a flow control mechanism to ensure ef

Figure 12-1: Flow Control Update LoopCreditsConsumedCounterCreditLimitData PacketFlowControlGatingLogic(CreditCheck)AllowIncrRxBufferData PacketCredit

counter. Essentially, this means the data sink knows the data source has less than a fullMAX_PAYLOAD worth of credits, and therefore is starving.b. Wh

Nevertheless, maintaining maximum throughput of completion data packets is important. Endpointsmust offer an infinite number of completion credits. En

Design Implementation132014.12.15UG-01097_avstSubscribeSend FeedbackCompleting your design includes additional steps to specify analog properties, pin

Datasheet12014.12.15UG-01097_avstSubscribeSend FeedbackStratix V Avalon-ST Interface for PCIe DatasheetAltera® Stratix® V FPGAs include a configurable

Understanding Physical Placement of the PCIe IP CoreFor more information about physical placement of the PCIe blocks, refer to the links below. Contac

a. Double-click in the Assignment Name column and scroll to the bottom of the availableassignments.b. Select VCCA_GXB Voltage.c. In the Value column,

Related InformationReset Sequence for Hard IP for PCI Express IP Core and Application Layer on page 7-3SDC Timing ConstraintsYou must include componen

set_false_path -from [get_clocks {reconfig_xcvr_clk}] -to [get_clocks {*|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout}]set_false_pa

Optional Features142014.12.15UG-01097_avstSubscribeSend FeedbackConfiguration via Protocol (CvP)The Hard IP for PCI Express architecture has an option

CvP has the following advantages:• Provides a simpler software model for configuration. A smart host can use the PCIe protocol and theapplication topo

Table 14-2: ECRC Operation on RX PathECRC Forwarding ECRC Check Enable(5)ECRC Status Error TLP Forward to Application LayerNoNonone No Forwardedgood N

Table 14-3: ECRC Generation and Forwarding on TX PathAll unspecified cases are unsupported and the behavior of the Hard IP is unknown.ECRC Forwarding

Hard IP Reconfiguration152014.08.18UG-01097_avstSubscribeSend FeedbackThe Stratix V Hard IP for PCI Express reconfiguration block allows you to dynami

Transceiver PHY IP Reconfiguration162014.12.15UG-01097_avstSubscribeSend FeedbackAs silicon progresses towards smaller process nodes, circuit performa

As this figure illustrates, the reconfig_to_xcvr[ <n> 70-1:0] and reconfig_from_xcvr[ <n> 46-1:0]buses connect the two components. You mus

10.From the Simulation list, select ModelSim®. From the Format list, select the HDL language youintend to use for simulation.11.Click Next to display

Figure 16-3: Specifying the Number of Transceiver Interfaces for Arria V GZ and Stratix V DevicesThe Transceiver Reconfiguration Controller includes a

Transceiver Reconfiguration Controller Connectivity for Designs UsingCvPIf your design meets the following criteria:• It enables CvP• It includes an a

Testbench and Design Example172014.12.15UG-01097_avstSubscribeSend FeedbackThis chapter introduces the Root Port or Endpoint design example including

Your Application Layer design may need to handle at least the following scenarios that are not possible tocreate with the Altera testbench and the Roo

The top-level of the testbench instantiates four main modules:• <qsys_systemname>— This is the example Endpoint design. For more information abo

Root Port TestbenchThis testbench simulates up to an ×8 PCI Express link using either the PIPE interfaces of the Root Portand Endpoints or the serial

The end point or Root Port variant is generated in the language (Verilog HDL or VHDL) that you selectedfor the variation file. The testbench files are

Figure 17-2: Top-Level Chaining DMA Example for SimulationRoot Complex CPURoot Port MemoryWriteDescriptorTableDataChaining DMAEndpoint MemoryAvalon-M

The following modules are included in the design example and located in the subdirectory<qsys_systemname>/testbench/<qsys_system_name>_tb/

The following modules are provided in both Verilog HDL:• altpcierd_example_app_chaining—This top level module contains the logic related to the Avalon

Files Generated for Altera IP CoresFigure 2-3: IP Core Generated FilesNotes:1. If supported and enabled for your IP variation2. If functional simulati

• altpcierd_read_dma_requester, altpcierd_read_dma_requester_128—For each descriptor located inthe altpcierd_descriptor FIFO, this module transfers da

Memory BAR MappingExpansion ROM BAR Not implemented by design example; behavior is unpredictable.I/O Space BAR (any) Not implemented by design example

Table 17-3: Bit Definitions for the Control Field in the DMA Write Control Register and DMA Read ControlRegisterBit Field Description16 Reserved —17MS

Addr Register NameBits[31:24] Bits[23:16] Bits[15:0]0x24DMA Wr Status LoTarget Mem AddressWidthWrite DMA Performance Counter. (Clockcycles from time D

Bit Field Description[15:0]Write DMA EPLASIndicates the number of the last descriptor completed by the writeDMA. For simultaneous DMA read and write t

Each subsequent descriptor consists of a minimum of four dwords of data and corresponds to one DMAtransfer. (A dword equals 32 bits.)Note: The chainin

The following table shows the layout of the descriptor fields following the descriptor header.Table 17-8: Chaining DMA Descriptor Format MapBits[31:22

Descriptor Field EndpointAccessRC Access DescriptionEPLAST_ENAR R/W This bit is OR’d with the EPLAST_ENA bit of the controlregister. When EPLAST_ENA i

• The chaining DMA writes the EPLast bit of the Chaining DMA Descriptor Tableaftercompleting the data transfer for the first and last descriptors.• Th

Table 17-12: Write Descriptor 1Offset in BFMShared MemoryValue DescriptionDW0 0x820 1,024 Transfer length in dwords and control bits as described inBi

Modifying the Example DesignTo use this example design as the basis of your own design, replace the Chaining DMA Example shown inthe following figure

Table 17-14: DMA Control Register Setup for DMA WriteOffset in DMAControl Register(BAR2)Value DescriptionDW0 0x0 3 Number of descriptors and control b

Table 17-16: Read Descriptor 1Offset in BFMShared MemoryValue DescriptionDW0 0x920 1,024 Transfer length in dwords and control bits as described in on

Offset in DMA ControlRegisters (BAR2)Value DescriptionDW1 0x14 0 BFM shared memoryupper address valueDW2 0x18 0x900 BFM shared memorylower address val

Figure 17-3: Root Port Design Example Root Port Variation(variation_name.v)Avalon-ST Interface(altpcietb_bfm_vc_intf)Test Driver(altpcietb_bfm_driver_

The top-level of the testbench instantiates the following key files:• altlpcietb_bfm_top_ep.v— this is the Endpoint BFM. This file also instantiates t

Figure 17-4: Root Port BFMBFM Shared Memory(altpcietb_bfm_shmem _common)BFM Log Interface(altpcietb_bfm_log_common)Root Port RTL Model (altpcietb_bfm_

• BFM Read/Write Request Functions(altpcietb_bfm_driver_rp.v)—These functions provide the basicBFM calls for PCI Express read and write requests. For

The ebfm_cfg_rp_ep executes the following steps to initialize the Configuration Space:1. Sets the Root Port Configuration Space to enable the Root Por

configuration is unlikely to be useful in real systems. If the procedure is unable to assign the BARs,it displays an error message and stops the simul

Offset (Bytes) Description+60 ReservedThe configuration routine does not configure any advanced PCI Express capabilities such as the AERcapability.Bes

Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as aSeparate ComponentYou can also instantiate the Stratix V Hard IP for PCI E

Figure 17-6: Memory Space Layout—No Limit Root Complex Shared MemoryUnusedUnusedConfiguration ScratchSpace Used byRoutines - NotWriteable by UserCal

Figure 17-7: I/O Address Space Root Complex Shared MemoryUnusedConfiguration ScratchSpace Used by BFMRoutines - NotWriteable by UserCalls or EndpointB

Verilog HDL include file altpcietb_bfm_driver_rp.v. The complete list of available procedures andfunctions is as follows:• ebfm_barwr—writes data from

Location altpcietb_bfm_rdwr.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory. The bar_table structure stores the add

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory. The bar_table structure stores th

Argumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory. The bar_table structure stores the address assigned toeach BAR so t

ebfm_cfgwr_imm_wait ProcedureThe ebfm_cfgwr_imm_wait procedure writes up to four bytes of data to the specified configurationregister. This procedure

Location altpcietb_bfm_driver_rp.vSyntax ebfm_cfgwr_imm_nowt(bus_num, dev_num, fnc_num, imm_regb_adr, regb_len, imm_data)Argumentsbus_numPCI Express b

Location altpcietb_bfm_driver_rp.vArgumentsbus_numPCI Express bus number of the target device.dev_numPCI Express device number of the target device.fn

Location altpcietb_bfm_driver_rp.vArgumentsbus_numPCI Express bus number of the target device.dev_numPCI Express device number of the target device.fn

Getting Started with the Configuration SpaceBypass Mode Qsys Example Design32014.08.18UG-01097_avstSubscribeSend FeedbackThis Qsys design example demo

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory. This routine populates the bar_ta

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory.bar_numBAR number to analyze.log2_

Constant DescriptionSHMEM_FILL_QWORD_INCSpecifies a data pattern of incrementing 64-bit qwords(0x0000000000000000, 0x0000000000000001,0x00000000000000

shmem_display Verilog HDL FunctionThe shmem_display Verilog HDL function displays a block of data from the BFM shared memory.Location altpcietb_bfm_dr

Related InformationShared Memory Constants on page 17-40shmem_chk_ok FunctionThe shmem_chk_ok function checks a block of BFM shared memory against a s

Table 17-21: Log MessagesConstant(MessageType)Description Mask BitNoDisplayby DefaultSimulationStops byDefaultMessagePrefixEBFM_MSG_DEBUGSpecifies deb

Constant(MessageType)Description Mask BitNoDisplayby DefaultSimulationStops byDefaultMessagePrefixEBFM_MSG_ERROR_FATAL_TB_ERRUsed for BFM test driver

ebfm_log_stop_sim Verilog HDL FunctionThe ebfm_log_stop_sim procedure stops the simulation.Location altpcietb_bfm_driver_rp.vSyntax Verilog VHDL: retu

Related InformationBFM Log and Message Procedures on page 17-43ebfm_log_open Verilog HDL FunctionThe ebfm_log_open procedure opens a log file of the s

Location altpcietb_bfm_driver_rp.vSyntax string:= himage(vec)ArgumentrangevecInput data type reg with a range of 7:0.ReturnrangestringReturns a 2-digi

Figure 3-1: Configuration Bypass Mode Qsys Example Design pcie_reconfig_driver_0to PCIe Root Portand Host SystemConfigurationBypass Top(cfbp_top)A

Locationaltpcietb_bfm_driver_rp.vSyntax string:= himage(vec)ArgumentrangevecInput data type reg with a range of 63:0.ReturnrangestringReturns a 16-dig

dimage3This function creates a three-digit decimal string representation of the input argument that can beconcatenated into a larger message string an

Locationaltpcietb_bfm_driver_rp.vReturnrangestringReturns a 5-digit decimal representation of the input argumentthat is padded with leading 0s if nece

chained_dma_test ProcedureThe chained_dma_test procedure is the top-level procedure that runs the chaining DMA read and thechaining DMA writeLocation

Location altpcietb_bfm_driver_rp.vSyntaxdma_wr_test (bar_table, bar_num, use_msi, use_eplast)Argumentsbar_tableAddress of the Endpoint bar_table struc

Location altpcietb_bfm_driver_rp.vSyntaxdma_set_header (bar_table, bar_num, Descriptor_size, direction, Use_msi,Use_eplast, Bdt_msb, Bdt_lab, Msi_numb

Location altpcietb_bfm_driver_rp.vArgumentsrc_addrAddress of the BFM shared memory that is being polled.rc_dataExpected data value of the that is bein

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory.bar_numBAR number to analyze.Bus_n

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemoryallowed_barsOne hot 6 bits BAR sele

Related InformationBFM Log and Message Procedures on page 17-43Debugging SimulationsYou can modify the following default testbench parameter settings

Figure 3-2: Configuration Bypass Qsys System1. Note the following parameter settings for the Configuration Space Bypass Example Design:• For the DUT,

Debugging182014.12.15UG-01097_avstSubscribeSend FeedbackAs you bring up your PCI Express system, you may face a number of issues related to FPGA confi

packets can be transmitted. If you encounter link training issues, viewing the actual data in hardwareshould help you determine the root cause. You ca

Possible Causes Symptoms and Root Causes Workarounds and SolutionsLink fails withLTSSM stuck inDetect.Active state(1)This behavior may be caused bya P

Possible Causes Symptoms and Root Causes Workarounds and SolutionsLink fails due tounstable rx_signaldetectConfirm that rx_signaldetectbus of the acti

Table 18-2: Link Hangs in L0Possible Causes Symptoms and Root Causes Workarounds and SolutionsAvalon-ST signalingviolates Avalon-STprotocolAvalon-ST p

Possible Causes Symptoms and Root Causes Workarounds and SolutionsMalformed TLP istransmittedRefer to the error log file to findthe last good packet t

• Avalon Interface Specifications• PCI Express Base Specification 2.1 or 3.0• Design Debugging Using the SignalTap II Embedded Logic AnalyzerSetting U

Disable the Scrambler for Gen1 and Gen2 SimulationsThe encoding scheme implemented by the scrambler applies a binary polynomial to the data stream toe

Transaction Layer Packet (TLP) Header FormatsA2014.12.15UG-01097_avstSubscribeSend FeedbackThe following figures show the header format for TLPs witho

Figure A-3: Memory Read Request, 64-Bit AddressingMemory Read Request, 64-Bit Addressing3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5

Table 3-1: Parameters to Specify on the Generation Tab in QsysParameter ValueCreate testbench Qsys system Standard, BFMs for standard Avalon interface

Figure A-6: I/O Read RequestI/O Read Request3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Figure A-9: Completion Locked without DataCompletion Locked without Data3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0

Figure A-11: Memory Write Request, 64-Bit AddressingMemory Write Request, 64-Bit Addressing3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6

Figure A-14: Completion with DataCompletion with Data3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0 0 1 0 0 1 0 1 0 0TC

Lane Initialization and ReversalB2014.12.15UG-01097_avstSubscribeSend FeedbackConnected components that include IP blocks for PCI Express need not sup

Figure B-1: Using Lane Reversal to Solve PCB Routing ProblemsThe following figure illustrates a PCI Express card with ×4 IP Root Port and a ×4 Endpoin

Additional InformationC2014.12.15UG-01097_avstSubscribeSend FeedbackRevision History for the Avalon-St InterfaceDate Version Changes Made2014.12.15 14

Date Version Changes Made2014.06.30 14.0Added the following new features to the Stratix V Hard IP for PCIExpress:• Added parameters to enable 256 comp

Date Version Changes Made• Added link to a Knowledge Base Solution that shows how toobserve the test_in bus for debugging.• Removed optional 125 MHz r

Date Version Changes Made2013.12.20 13.1 Made the following changes:• Divided user guide into 3 separate documents by interface type.• Added Design Im

Understanding Simulation Log File GenerationStarting with the Quartus II 14.0 software release, simulation automatically creates a log file, altpcie_m

Date Version Changes Made2013.05.06 13.0 • Added support for Configuration Space Bypass Mode, allowingyou to design a custom Configuration Space and s

Contact (1)Contact Method AddressTechnical support Website www.altera.com/supportTechnical trainingWebsite www.altera.com/trainingEmail custrain@alte

Visual Cue Meaningitalic type Indicates variables. For example, n + 1.Variable names are enclosed in angle brackets (< >).For example, <file

Visual Cue Meaningm The multimedia icon directs you to a relatedmultimedia presentation.c A caution calls attention to a condition or possiblesituatio

Link Width×1 ×2 ×4 ×8PCI Express Gen3(8.0 Gbps)7.87 15.75 31.51 63Refer to the AN 690: PCI Express DMA Reference Design for Stratix V Devices for more

1. To observe the simulation, on the ModelSim View menu, select wave. Then add some key interfaces tothe wave window. The following four interfaces un

Figure 3-4: Configuration Read to Function 0RxStMask_oRxStSop_iRxStEop_iRxStValid_iRxStReady_oRxStData_i[255:0]cfg_addr_o[31:0]cfg_rden_ocfg_wren_ocfg

The preceding timing diagram illustrates the following sequence of events:1. The Application Layer indicates it is ready to receive requests by assert

Figure 3-5: Configuration Write to Function 0RxStMask_oRxStSop_iRxStEop_iRxStValid_iRxStReady_oRxStData_i[255:0cfg_addr_o[31:0]cfg_rden_ocfg_wren_cfg_

Figure 3-6: Timing for Memory Write and Read of Function 1RxStMask_oRxStSop_iRxStEop_iRxStValid_iRxStReady_oTxStReady_iTxStSop_oTxStEop_oTxStValid_ or

The timing diagram illustrates the following sequence of events:1. The Application Layer indicates it is ready to receive requests by asserting RxSTRe

# INFO: 48089 ns RP LTSSM State: L0 # INFO: 48133 ns EP LTSSM State: L0 # INFO: 48226 ns Configuring Bus 000, Device 000, Function 00 # INFO: 48226 ns

# INFO: 73354 ns TASK:my_test Memory write burst at addr=0x08# with wdata=0x10203040 # INFO: 73362 ns TASK:my_test => 2.21 Memory Read burst# INF

Parameter Settings42014.08.18UG-01097_avstSubscribeSend FeedbackSystem SettingsTable 4-1: System Settings for PCI ExpressParameter Value DescriptionNu

Parameter Value DescriptionRX Buffer creditallocation -performance forreceived requestsMinimumLowBalancedHighMaximumDetermines the allocation of poste

Table 1-2: Feature Comparison for all Hard IP for PCI Express IP CoresThe table compares the features of the four Hard IP for PCI Express IP Cores.Fea

Parameter Value Description• Minimum—configures the minimum PCIe specificationallowed for non-posted and posted request credits, leavingmost of the RX

Parameter Value DescriptionReference clockfrequency100 MHz125 MHzThe PCI Express Base Specification 3.0 requires a100 MHz ±300 ppm reference clock. Th

Parameter Value DescriptionEnable configu‐ration via PCIExpress (CvP)On/Off When On, the Quartus II software places the Endpoint in thelocation requir

Table 4-2: BAR RegistersParameter Value DescriptionType Disabled64-bit prefetchable memory32-bit non-prefetchable memory32-bit prefetchable memoryI/O

Base and Limit Registers for Root PortsTable 4-3: Base and Limit RegistersThe following table describes the Base and Limit registers which are availab

Register Name Range Default Value DescriptionClass code 24 bits 0x00000000 Sets the read-only value of the Class Code register.Address offset: 0x008.S

Parameter Possible Values Default Value DescriptionNumber ofTagssupported326432 Indicates the number of tags supported for non-postedrequests transmit

Parameter Possible Values Default Value Description• 0111 Ranges A, B, and C• 1110 Ranges B, C and D• 1111 Ranges A, B, C, and DAll other values are r

Parameter Value Default Value DescriptionTrack RXcompletionbufferoverflow onthe Avalon-ST interfaceOn/Off Off When On, the core includes the rxfx_cplb

MSI and MSI-X CapabilitiesTable 4-8: MSI and MSI-X Capabilities Parameter Value DescriptionMSI messagesrequested1, 2, 4, 8, 16, 32 Specifies the numbe

Feature Avalon‑ST Interface Avalon‑MMInterfaceAvalon‑MM DMA Avalon‑ST Interface with SR-IOVTransactionLayer Packettype (TLP) • Memory ReadRequest• Mem

Slot CapabilitiesTable 4-9: Slot Capabilities Parameter Value DescriptionUse Slot register On/Off The slot capability is required for Root Ports if a

Power ManagementTable 4-10: Power Management ParametersParameter Value DescriptionEndpoint L0sacceptablelatencyMaximum of 64 nsMaximum of 128 nsMaximu

Vendor Specific Extended Capability (VSEC)Table 4-11: VSECParameter Value DescriptionUser ID registerfrom the VendorSepcific ExtendedCapabilityCustom

Interfaces and Signal Descriptions52014.12.15UG-01097_avstSubscribeSend FeedbackFigure 5-1: Avalon-ST Hard IP for PCI Express Top-Level Signalsrx_st_d

Avalon‑ST RX InterfaceThe following table describes the signals that comprise the Avalon-ST RX Datapath. The RX data signalcan be 64, 128, or 256 bits

Signal Direction DescriptionFor 128-bit data, only bit 0 applies; this bit indicates whether theupper qword contains data. For 256-bit data single pac

Signal Direction Descriptionrx_st_valid Output Clocks rx_st_data into the Application Layer. Deasserts within2 clocks of rx_st_ready deassertion and

Signal Direction Descriptionrx_st_bar[7:0] Output The decoded BAR bits for the TLP. Valid for MRd, MWr, IOWR, andIORD TLPs. Ignored for the completion

Signal Direction Descriptionrx_st_be[<n>-1:0] Output Byte enables corresponding to the rx_st_data. The byte enablesignals only apply to PCI Expr

Data Alignment and Timing for the 64‑Bit Avalon‑ST RX InterfaceTo facilitate the interface to 64-bit memories, the Stratix V Hard IP for PCI Express a

Feature Avalon‑ST Interface Avalon‑MMInterfaceAvalon‑MM DMA Avalon‑ST Interface with SR-IOVOut-of-ordercompletions(transparent tothe ApplicationLayer)

Packet TLPData1 pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4Data2 pcie_data_byte11, pcie_data_byte10, pcie_data_byte9, pcie_data

Figure 5-4: 64-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with QwordAligned AddressIn the following figure, rx_st_be[7

Figure 5-6: 64-Bit Avalon-ST rx_st_data<n> Cycle Definitions for 4-Dword Header TLPs with Non-Qword AddressesThe following figure shows the mapp

Figure 5-8: 4-Bit Avalon-ST Interface Back-to-Back TransmissionThe following figure illustrates back-to-back transmission on the 64-bit Avalon-ST RX i

Data Alignment and Timing for the 128‑Bit Avalon‑ST RX InterfaceFigure 5-9: 128-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header

Figure 5-10: 128-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with non-Qword Aligned AddressesThe following figure shows

Figure 5-12: 128-Bit Avalon-ST rx_st_data Cycle Definition for 4-Dword Header TLPs with QwordAligned AddressesThe following figure shows the mapping o

Figure 5-14: 128-Bit Avalon-ST Interface Back-to-Back TransmissionThe following figure illustrates back-to-back transmission on the 128-bit Avalon-ST

Single packer per cycle mode requires simpler Application Layer packet decode logic on the TX and RXpaths because packets always start in the lower 12

Tradeoffs to Consider when Enabling Multiple Packets per CycleIf you enable Multiple Packets Per Cycle under the Systems Settings heading, a TLP can s

• V-Series Avalon-MM DMA Interface for PCIe Solutions User GuideRelease InformationTable 1-3: Hard IP for PCI Express Release InformationItem Descript

rx_st_sop[0]rx_st_eop[0]rx_st_sop[1]rx_st_eop[1]rx_st_data[255:0]rx_st_be[31:0]rx_st_bardec1[7:0]rx_st_bardec2[7:0]rx_st_empty[1:0]rx_st_errrx_st_mask

Table 5-4: 64-, 128-, or 256‑Bit Avalon-ST TX DatapathSignal Direction Descriptiontx_st_data[<n>-1:0]Input Data for transmission. Transmit data

Signal Direction Descriptiontx_st_ready Output Indicates that the Transaction Layer is ready to accept data fortransmission. The core deasserts this s

Signal Direction Descriptionwords that contain data, resulting in the following encodings forthe 128-and 256-bit interfaces:128-Bit interface:tx_st_em

Signal Direction Descriptiontx_st_errInput Indicates an error on transmitted TLP. This signal is used tonullify a packet. It should only be applied to

Signal Direction Descriptiontx_cred_fchipcons[5:0]Output Asserted for 1 cycle each time the Hard IP consumes a credit.These credits are from messages

Signal Direction Descriptionko_cpl_spc_header[7:0]Output The Application Layer can use this signal to build circuitry toprevent RX buffer overflow for

Data Alignment and Timing for the 64‑Bit Avalon‑ST TX InterfaceFigure 5-19:The following figure illustrates the mapping between Avalon-ST TX packets a

Data0 = {pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0}Data1 = {pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte

Figure 5-24: 64-Bit Back-to-Back Transmission on the TX InterfaceThe following figure illustrates back-to-back transmission of 64-bit packets with no

ConfigurationsThe Stratix V Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stackincluding the following layers:• Ph

Figure 5-26: 128-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with non-QwordAligned AddressThe following figure shows the mapping

Header 3 Data 2Header 2 Data 1Data nHeader 1 Data 0Data n-1Header 0Data n-2pld_clktx_st_validtx_st_data[127:96]tx_st_data[95:64]tx_st_data[63:32]tx_st

pld_clktx_st_data[127:0]tx_st_soptx_st_eoptx_st_emptytx_st_readytx_st_validtx_st_err000 CC... CC... CC... CC... CC... CC... CC... CC... CC... CC... CC

Figure 5-31: 256-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with QwordAddressesThe following figure illustrates the layout of he

Figure 5-32: 256-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with QwordAddresses01 10clktx_st_data[63:0]Aligned Data Unaligned Da

Related InformationTradeoffs to Consider when Enabling Multiple Packets per Cycle on page 5-17Root Port Mode Configuration RequestsIf your Application

Related InformationClocks on page 7-5Reset, Status, and Link Training SignalsRefer to Reset and Clocks for more information about the reset sequence a

Signal Direction DescriptionFor example, if you are using the Hard IP instance in the bottomleft corner of the device, you must connect pin_perst toNP

Table 5-7: Status and Link Training SignalsSignal Direction Descriptionserdes_pll_lockedOutput When asserted, indicates that the PLL that generates th

Signal Direction Descriptionlane_act[3:0] Output Lane Active Mode: This signal indicates the number of lanes thatconfigured during link training. The

PCIe LinkPCIe Hard IPRPSwitchPCIeHard IPRPUser ApplicationLogicPCIe Hard IPEPPCIe LinkPCIe LinkUser ApplicationLogicAltera FPGA Hard IP for PCI Expres

Signal Direction Description• 11011: Recovery.Equalization, Phase 0• 11100: Recovery.Equalization, Phase 1• 11101: Recovery.Equalization, Phase 2• 111

Signal I/O Descriptionderr_rpl Output Indicates an uncorrectable error in the retry buffer. This signal isfor debug only. (1)derr_cor_ext_rpl0 Output

Signal Direction Descriptionapp_msi_num[4:0]Input MSI number of the Application Layer. This signal provides thelow order message data bits to be sent

Completion Side Band SignalsThe following table describes the signals that comprise the completion side band signals for the Avalon-ST interface. The

Signal DirectionDescription• cpl_err[0]: Completion timeout error with recovery. This signalshould be asserted when a master-like interface has perfor

Signal DirectionDescription• cpl_err[4]: Unsupported Request (UR) error for posted TLP.The Application Layer asserts this signal to treat a posted req

Configuration Space Bypass Mode Interface SignalsIn Configuration Space Bypass mode, the soft Configuration Space exchanges control and status informa

Signal Name Direction Descriptiontx_req_pmInput Assert this signal to request that the TX Data Link Layer send aPower Management Data Link Layer Packe

Signal Name Direction Descriptionlink3_ctl[1]Input Link Control 3 Register bit[1]: Link Equalization RequestInterrupt Enable. When set to 1, enables t

Signal Name Direction Descriptionlink_trainOutput Reported as Bit 10 of the Link Status Register. Whenasserted, indicates that the link is training.l0