Altera RapidIO II MegaCore Function Bedienungsanleitung PDF herunterladen (Seite 215)

Additional Information Info–3

Document Revision History

August 2014 Altera Corporation RapidIO II MegaCore Function

User Guide

June 2014,

continued

Continued on

14.0

■ Corrected descriptions of

IN_ERR_STOP

and

OUT_ERR_STOP

fields of the

Port 0 Error

and Status CSR

(offset 0x158, Table 6–14 on page 6–12) to state that the three control

symbols unexpected

packet-accepted

, unexpected

packet-retry

, and unexpected

packet-not-accepted

, set the

OUT_ERR_STOP

bit (and take the state machine into the

corresponding state) and not the

IN_ERR_STOP

bit as was previously indicated.

■ Replaced “Serial RapidIO” with “RapidIO”. The RapidIO II IP core supports only the Serial

RapidIO specification.

■ Clarified in Table 5–6 on page 5–4 that the user must implement the logic to utilize the

link_req_reset_device_received

output signal to reset the IP core.

■ Fixed descriptions of

OUTBOUND_ACKID

and

OUTSTANDING_ACKID

fields of the

Port 0

Local AckID CSR

(0x148 , Table 6–12 on page 6–10). The user cannot write directly to

the

OUTSTANDING_ACKID

field. Instead, if software writes to the

OUTBOUND_ACKID

field,

the new value appears in both the

OUTBOUND_ACKID

field and the

OUTSTANDING_ACKID

field. The user can write to

OUTBOUND_ACKID

to force retransmission of outstanding

unacknowledged packets,

■ Corrected erroneous statement that software can reset the

REMOTE_TX_EMPH_ENABLE

bit

in the

Port 0 Control 2 CSR

(offset 0x154, Table 6–13 on page 6–10). This bit cannot

be reset, and remote transmit emphasis control is always turned on.

■ Corrected description of

PORT_ERR

field of Port 0 Error and Status CSR (offset 0x158,

Table 6–14 on page 6–12) and list of events that cause stored packets to be lost (in

“Low-Level Interface Transmitter” on page 4–75): removed erroneous indication that

port_status

value of Error can lead to a fatal error. The IP core has no specific reaction

port_status

being set to Error. Instead, the user can identify this situation from the

Port 0 Link Maintenance Response

CSR’s

PORT_STATUS

field, and handle it in

software.

■ Added new information to the description of the

Logical/Transport Layer Address

Capture CSR

(offset 0x314, Table 6–69 on page 6–47): in the case of a

MAINTENANCE

Response with Error status, the

ADDRESS

field now captures the

config_offset

value

from the original request.

■ Clarified in “Clocking and Reset Structure” on page 4–3 that the transceiver reference

clock (

tx_pll_refclk)

and the system clock (

sys_clk

) inputs must be generated from

the same clock source.

■ Clarified in Appendix B, Differences Between RapidIO II MegaCore Function v12.1 and

RapidIO MegaCore Function v12.1:

■ In the RapidIO II IP core, you cannot independently select whether or not to support

port-write

transactions. If you include a Maintenance module in your design, your

IP core supports

port-write

transactions.

■ In the RapidIO II IP core (in contrast to the RapidIO IP core) on the Avalon-ST pass-

through interface in the RX direction only, the sourceID and destinationID fields in

gen_rx_hd_data

are 16 bits wide even if the device ID width for the IP core variation

is 8 bits. However, in the TX direction, as in the RapidIO IP core, the sourceID and

destinationID field width depends on the device ID width.

■ Since v13.0, RapidIO IP core has 2x variations, which has same Avalon-MM I/O

Logical layer data bus width as the 4x variations.

■ In Sending Link-Request Reset-Device on Fatal Errors parameter entry, added

information for full comparison.

■ Corrected descriptions of Port 0 Packet Capture 1-3 CSRs to no longer erroneously

indicate their values are affected when the

Port 0 Attributes Capture

CSR

INFO_TYPE

field value is Long control symbol.

Date Version Changes

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