Altera Stratix V Avalon-ST Bedienungsanleitung

Stratix V Avalon-ST Interface with SR-IOV PCIe SolutionsUser GuideLast updated for Altera Complete Design Suite: 14.1SubscribeSend FeedbackUG-01097_sr

Related InformationFitter Resources ReportsRecommended Speed GradesTable 1-6: Stratix V Recommended Speed Grades for All SR-IOV ConfigurationsAltera r

Uncorrectable Error Mask RegisterTable 5-42: Uncorrectable Error Mask Register - 0x148 (ARI supported) or 0x108 (ARI not supported)Bits Register Descr

Bits Register DescriptionDefault ValueAccess[18] Malformed TLP Received 1RW[17] Receiver Overflow 1RW[16] Unexpected Completion was received0RW[15] Co

Bits Register DescriptionDefault ValueAccess[0] When set, indicates a Receiver Error0RW1CRelated InformationPCI Express Base Specification 2.1 or 3.0C

Table 5-46: Virtual Function Registers - Differences from PFAddress(hex)Name Description0x000 Vendor ID and Device IDRegisterVendor ID Register and De

Address(hex)Name Description0x084 PCI Express Device Capabil‐ities RegisterPCI Express Device Capabilities Register. The VF DeviceCapabilities Registe

Bits Register Description Default Value Access[3:0] Reserved. 0 RO[4] Indicates the presence of PCI Extended Capabilities. This bit ishardwired to 1.0

Bits Register Description Default Value Access[15] Function-Level Reset. Writing a 1 to this bit generates a Function-Level Reset for this VF. Only fu

Reset and Clocks62014.12.15UG-01097_sriovSubscribeSend FeedbackStratix V Hard IP for PCI Express IP Core includes both a soft reset controller and a h

Figure 6-1: Reset Controller Block DiagramExample Designaltpcie_dev_hip_<if>_hwtcl.valtpcied_<dev>_hwtcl.svTransceiver HardReset Logic/Sof

Reset Sequence for Hard IP for PCI Express IP Core and Application LayerFigure 6-2: Hard IP for PCI Express and Application Logic Reset SequenceYour A

• Is your design an Endpoint or Root Port?• What Generation do you intend to implement?• What link width do you intend to implement?• What bandwidth d

Figure 6-3: RX Transceiver Reset Sequencebusy_xcvr_reconfigrx_pll_lockedrx_analogresetltssmstate[4:0]txdetectrx_loopbackpipe_phystatuspipe_rxstatus[2:

For descriptions of the available reset signals, refer to Reset Signals, Status, and Link Training Signals.Function Level Reset (FLR)The following seq

Figure 6-5: Clock Domains and Clock Generation for the Application LayerThe following illustrates the clock domains when using coreclkout_hip to drive

coreclkout_hipTable 6-3: Application Layer Clock Frequency for All Combinations of Link Width, Data Rate andApplication Layer Interface WidthsThe core

Clock SummaryTable 6-4: Clock SummaryName Frequency Clock Domaincoreclkout_hip62.5, 125 or 250 MHz Avalon-ST interface between the Transaction andAppl

Programming and Testing SR-IOV Bridge MSIInterrupts72014.12.15UG-01097_sriovSubscribeSend FeedbackRelated InformationInterrupt Interface on page 4-14S

Setting Up and Verifying MSI Interrupts. Perform them once, during or after enumeration.1. Disable legacy interrupts by setting Interrupt Disable bit

11.Send a Configuration Write Request to clear the MSI mask bit for the selected function and interruptnumber.12.Verify that the SR-IOV bridge does no

Error Handling82014.12.15UG-01097_sriovSubscribeSend FeedbackEach PCI Express compliant device must implement a basic level of error management and ca

Physical Layer ErrorsTable 8-2: Errors Detected by the Physical LayerThe following table describes errors detected by the Physical Layer. Physical Lay

Getting Started with the SR-IOV DMA ExampleDesign22014.12.15UG-01097_sriovSubscribeSend FeedbackThe SR-IOV example design consists of an SR-IOV bridge

Transaction Layer ErrorsTable 8-4: Errors Detected by the Transaction LayerError Type DescriptionPoisoned TLP received Uncorrectable(non-fatal)This er

Error Type DescriptionCompletion timeout Uncorrectable(non-fatal)This error occurs when a request originating from theApplication Layer does not gener

Error Type DescriptionMalformed TLP Uncorrectable(fatal)This error is caused by any of the following conditions:• The data payload of a received TLP e

Poisoned TLPs can also set the parity error bits in the PCI Configuration Space Status register.Table 8-5: Parity Error ConditionsStatus Bit Condition

Figure 8-2: Correctable Error Status RegisterThe default value of all the bits of this register is 0. An error status bit that is set indicates that t

IP Core Architecture92014.12.15UG-01097_sriovSubscribeSend FeedbackThe Stratix V Hard IP for PCI Express with SR-IOV implements the complete PCI Expre

Table 9-1: Application Layer Clock FrequenciesLanes Gen1 Gen2 Gen3×2N/A N/A125 MHz @ 128 bits×4N/A125 MHz @ 128 bits 250 MHz @ 128 bits or125 MHz @ 25

InterruptsThe Hard IP for PCI Express offers the following interrupt mechanisms:• Message Signaled Interrupts (MSI)— MSI uses the Transaction Layer&ap

Figure 9-2: Data Link LayerTo Transaction LayerTx Transaction LayerPacket Description & DataTransaction LayerPacket GeneratorRetry BufferTo Physic

• ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and generates the sequencenumber of transmitted packets.• Transaction Layer Packet Checker—T

Figure 2-1: SR-IOV Example Design Block DiagramHard IP for PCI ExpressSR-IOV BridgeRd_DC0 Rd_DC1 Rd_DC2 Rd_DC3Read DMA RouterAPPs - sriov_dma_app_g3x8

Figure 9-3: Physical Layer ArchitectureScrambler8B10BEncoderLane nTX+ / TX-Scrambler8B10BEncoderLane 0TX+ / TX-Descrambler8B10BDecoderLane nRX+ / RX-E

The PHYMAC block comprises four main sub-blocks:• MAC Lane—Both the RX and the TX path use this block.• On the RX side, the block decodes the Physical

The SR-IOV processes memory requests, Completions and messages received from the link. It passesthem to the Application Layer unmodified, using the Av

BAR Logic DetailsThe BAR block includes the following functions:• Compares the addresses of received memory transactions to the BAR settings for the t

Function Number Assignments Function Type6Virtual Function 5 (optional)7Virtual Function 6 (optional)Table 9-3: Function Address Map: Two PFs and No A

Table 9-5: Function Address Map: Two PFs and ARIFunction Number Assignments Function Type0 Physical Function 01 Physical Function 12–127 Reserved128 V

Design Implementation102014.12.15UG-01097_sriovSubscribeSend FeedbackCompleting your design includes additional steps to specify analog properties, pi

a. Double-click in the Assignment Name column and scroll to the bottom of the availableassignments.b. Select VCCA_GXB Voltage.c. In the Value column,

Related InformationReset Sequence for Hard IP for PCI Express IP Core and Application Layer on page 6-3SDC Timing ConstraintsNote: You may need to cha

Transceiver PHY IP Reconfiguration112014.12.15UG-01097_sriovSubscribeSend FeedbackAs silicon progresses towards smaller process nodes, circuit perform

Qsys Subsystem Descriptionwrdc_ctl_256b.qsys This subsystem implements the Write Descriptor Controller for 4 WriteDMA channels.Note: File names that i

As this figure illustrates, the reconfig_to_xcvr[ <n> 70-1:0] and reconfig_from_xcvr[ <n> 46-1:0]buses connect the two components. You mus

Figure 11-3: Specifying the Number of Transceiver Interfaces for Arria V GZ and Stratix V DevicesThe Transceiver Reconfiguration Controller includes a

Transceiver Reconfiguration Controller Connectivity for Designs UsingCvPIf your design meets the following criteria:• It enables CvP• It includes an a

Debugging122014.12.15UG-01097_sriovSubscribeSend FeedbackAs you bring up your PCI Express system, you may face a number of issues related to FPGA conf

packets can be transmitted. If you encounter link training issues, viewing the actual data in hardwareshould help you determine the root cause. You ca

Possible Causes Symptoms and Root Causes Workarounds and SolutionsLink fails withLTSSM stuck inDetect.Active state(1)This behavior may be caused bya P

Possible Causes Symptoms and Root Causes Workarounds and SolutionsLink fails due tounstable rx_signaldetectConfirm that rx_signaldetectbus of the acti

Using the PIPE Interface for Gen1 and Gen2 VariantsRunning the simulation in PIPE mode reduces simulation time and provides greater visibility.Complet

Use Third-Party PCIe AnalyzerA third-party logic analyzer for PCI Express records the traffic on the physical link and decodes traffic,saving you the

Transaction Layer Packet (TLP) Header FormatsA2014.12.15UG-01097_sriovSubscribeSend FeedbackThe following figures show the header format for TLPs with

6. Specify the following parameters:Table 2-1: Parameters to Specify on the Generation Menu in QsysParameter ValueTestbench SystemCreate testbench Qsy

Figure A-3: Memory Read Request, 64-Bit AddressingMemory Read Request, 64-Bit Addressing3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5

Figure A-6: I/O Read RequestI/O Read Request3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Figure A-9: Completion Locked without DataCompletion Locked without Data3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0

Figure A-12: Configuration Write Request Root Port (Type 1)Configuration Write Request Root Port (Type 1)3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5

Figure A-15: Completion Locked with DataCompletion Locked with Data3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0 0 1

Additional InformationB2014.12.15UG-01097_sriovSubscribeSend FeedbackSR-IOV PCIe Revision HistoryDate Version Changes Made2014.12.15 14.1 Made the fol

Contact (1)Contact Method AddressTechnical trainingWebsite www.altera.com/trainingEmail [email protected] literature Website www.altera.com/

Visual Cue Meaningitalic type Indicates variables. For example, n + 1.Variable names are enclosed in angle brackets (< >).For example, <file

Visual Cue Meaningm The multimedia icon directs you to a relatedmultimedia presentation.c A caution calls attention to a condition or possiblesituatio

Parameter ValuePathworking_dir/top10.Click Generate.11.On the File menu, click Save.Understanding the Generated Files and DirectoriesTable 2-3: Qsys G

Understanding the DMA FunctionalityThe following figures illustrate the DMA functionality using numbered steps.Figure 2-3: Steps to Fetch Descriptor T

Figure 2-4: Steps To Perform a DMA Readsriov_top_dma_gen3_x8_256.qsysHard IP for PCI ExpressSR-IOV BridgeRd_DC0 Rd_DC1 Rd_DC2 Rd_DC3Read DMA RouterAPP

Figure 2-5: Steps To Perform a Write DMAsriov_top_dma_gen3_x8_256.qsysStratix V Hard IP for PCI ExpressSR-IOV BridgeRd_DC0 Rd_DC1 Rd_DC2 Rd_DC3Read DM

Datasheet12014.12.15UG-01097_sriovSubscribeSend FeedbackStratix V Avalon-ST Interface with SR-IOV for PCIe DatasheetAltera® Stratix® V FPGAs include a

These files specify Synopsys Design Constraints, Quartus II design constraints, and top-levelconnectivity.3. On the Quartus II file menu, select the N

Parameter Settings32014.12.15UG-01097_sriovSubscribeSend FeedbackSystem SettingsTable 3-1: System Settings for PCI ExpressParameter Value DescriptionL

Parameter Value DescriptionReference clockfrequency100 MHz The PCI Express Base Specification 3.0 requires a100 MHz ±300 ppm reference clock. The 125

Parameter Value Description• Minimum RX Buffer credit allocation—configures theminimum PCIe specification allowed for non-posted andposted request cre

Parameter Value DescriptionEnable byteparity ports onAvalon-STinterfaceOn/Off When on, the RX and TX datapaths are parity protected.Parity is odd.This

Parameter Value DescriptionEnable SR-IOVSupportOn/OffTurn this option on to include the SR-IOV functionality.Enable Alterna‐tive Routing-ID(ARI) suppo

Parameter Value DescriptionPrefetch‐ablePrefetchableNon-PrefetchableDefining memory as prefetchable allows data in theregion to be fetched ahead antic

Register Name Range Default Value DescriptionSubsystemDevice ID16 bits 0x00000000 Sets the read-only value of the Subsystem Device IDregister in the P

Parameter Value DescriptionMSI-X TableBAR Indicator[2:0] Specifies which one of a function’s BAR number. This field isread-only. For 32-bit BARs, the

Device CapabilitiesParameter PossibleValuesDefaultValueDescriptionMaximumpayload size128 bytes256 bytes128 bytes Specifies the maximum payload size su

Table 1-1: PCI Express Data ThroughputThe following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for supportedli

Parameter PossibleValuesDefaultValueDescriptionExtendedtag supportOn/Off OnWhen enabled, the Application Layer supports up to 256 tagsfor non-posted r

Parameter Value Default Value DescriptionTrack RXcompletionbufferoverflow onthe Avalon-ST interfaceOn/Off Off When On, the core includes the rxfx_cplb

Parameter Value DescriptionSurprise downreportingOn/OffWhen this option is On, a downstream port supports theoptional capability of detecting and repo

Parameter Value DescriptionSlot power scale0–3Specifies the scale used for the Slot power limit. The followingcoefficients are defined:• 0 = 1.0x• 1 =

Parameter Value DescriptionEndpoint L1acceptablelatencyMaximum of 1 usMaximum of 2 usMaximum of 4 usMaximum of 8 usMaximum of 16 usMaximum of 32 usNo

Simulation OptionsTable 3-11: Simulation OptionsParameter Value Default Value DescriptionEnableDMASimulationOn/OffOnEnable DMA simulation or target si

Interfaces and Signal Descriptions42014.12.15UG-01097_sriovSubscribeSend Feedbacktx_out0[<n>-1:0]rx_in0[<n>-1:0]Hard IP SerialHard IP Rese

Avalon-ST TX InterfaceTable 4-1: 128- or 256-Bit Avalon-ST TX DatapathSignal Direction Descriptiontx_st_data[<n>-1:0]Input Data for transmission

Signal Direction Descriptiontx_st_valid (3)Input Clocks tx_st_data to the core when tx_st_ready is alsoasserted. Between tx_st_sop and tx_st_eop, tx_s

Table 4-2: Component Specific TX Credit SignalsSignal Direction Descriptiontx_cred_datafccp[11:0]Output Data credit limit for the received FC completi

• Support for Configuration Space Bypass Mode, allowing you to design a custom Configuration Spaceand support multiple functions.• Support for Gen3 PI

Signal Direction Descriptiontx_cred_hdrfccp[7:0]Output Header credit limit for the FC completions. Each credit is 20bytes.tx_cred_hdrfcnp[7:0]Output H

Signal Direction Descriptionqwords contain data, resulting in the following encodings for the128-and 256-bit interfaces:• 128-Bit interface:• rx_st_em

Signal Direction Descriptionrx_st_errOutput Indicates that there is an uncorrectable error correction coding(ECC) error in the internal RX buffer. Act

BAR Hit SignalsSignal Direction Descriptionrx_st_bar_hit_tlp0[7:0]rx_st_bar_hit_tlp1[7:0]Output Identifies the matching BAR for the TLP driven on the

Signal Direction Descriptionrx_st_mask InputThe Application Layer asserts this signal to tell the Hard IP tostop sending non-posted requests. This sig

Signal Direction Descriptionmem_space_en_pf[<n>-1:0]Output The PF0 and PF1 PCI Command Registers drive the MemorySpace Enable bit.bus_master_en_

Table 4-5: Completion Signals for the Avalon-ST InterfaceSignal DirectionDescriptioncpl_err[6:0]Input Completion error. This signal reports completion

Signal DirectionDescription• cpl_err[4]: Unsupported Request (UR) error for posted TLP. TheApplication Layer asserts this signal to treat a posted req

Signal DirectionDescriptionko_cpl_spc_header]7:0]Output The Application Layer can use this signal to build circuitry to prevent RXbuffer overflow for

Table 4-7: Function-Level Reset InterfaceSignal Direction Descriptionflr_active_pf[<n>-1:0]Output When asserted, indicates the PF FLR field (bit

Feature Avalon‑ST Interface Avalon‑MMInterfaceAvalon‑MM DMA Avalon‑ST Interface with SR-IOVTransactionLayer Packettype (TLP) • Memory ReadRequest• Mem

This interface also includes signals to set and clear the individual bits in the MSI Pending Bit Register.Table 4-8: MSI InterruptsSignal Direction De

Signal Direction Descriptionapp_msi_num[4:0] Input Identifies the MSI interrupt type to be generated. Provides thelow-order message data bits to be se

Figure 4-1: Timing Diagram for MSI Interrupt Generationpld_clkMSI Function NoMSI NumberStatusMSI TCapp_msi_reqapp_msi_req_fn[7:0]app_msi_num[4:0]app_m

Signal Direction Descriptionapp_msix_addr[63:0] Input The Application Layer drives the address for the MSI-X postedwrite TLP on this input. Driven in

Figure 4-3: Timing Diagram for MSI-X Interrupt Generationpld_clkMSI-X Function NoMSI-X AddressMSI-X TCapp_msix_reqapp_msi_req_fn[7:0]app_msix_addr[63:

Signal Direction Descriptionapp_int_pend_status[1:0]Input The Application Layer must drive each of these inputs with theinterrupt pending status of th

Figure 4-6: MSI-X Interrupt ComponentsHostRXTXRXTXPCIe with SR-IOV BridgeMSI-X TableIRQProcessorMSI-X PBAIRQ SourceApplication LayerHost SW Programs

Figure 4-8: MSI-X PBA TablePending Bits 0 through 63Pending Bits 64 through 127Pending Bits ((N - 1) div 64) × 64 through N - 1QWORD 0QWORD 1QWORD ((

The LMI interface is synchronized to pld_clk and runs at frequencies up to 250 MHz. The LMI address isthe same as the Configuration Space address. The

Figure 4-10: LMI Readpld_clklmi_rdenlmi_addr[11:0]lmi_dout[31:0]lmi_acklmi_addr[8:0]Figure 4-11: LMI WriteThe following figure illustrates the LMI wri

Feature Avalon‑ST Interface Avalon‑MMInterfaceAvalon‑MM DMA Avalon‑ST Interface with SR-IOVOut-of-ordercompletions(transparent tothe ApplicationLayer)

Signal Direction Descriptionpin_perstInput Active low reset from the PCIe reset pin of the device.Refer to the appropriate Stratix V device pinout for

Signal Direction Descriptionreset_statusOutput Active high reset status signal. When asserted, this signalindicates that the Hard IP clock is in reset

Signal Direction DescriptiondlupOutput When asserted, indicates that the Hard IP block is in the DataLink Control and Management State Machine (DLCMSM

Signal Direction Descriptionltssmstate[4:0]Output LTSSM state: The LTSSM state machine encoding defines thefollowing states:• 00000: Detect.Quiet• 000

Signal Direction Descriptiontx_par_err[1:0]Output When asserted for a single cycle, indicates a parity error duringTX TLP transmission. These errors a

Table 4-16: Number of Logical and Physical Reconfiguration InterfacesVariant Logical InterfacesGen2 ×4 5Gen1 and Gen2 ×8 10Gen3 ×4 6Gen3 ×8 11For more

devices. Note that the bottom left IP core includes the CvP functionality. The other Hard IP blocks do notinclude the CvP functionality.Figure 4-13: S

Channel Placement in Arria V GZ and Stratix V GX/GT/GS DevicesFigure 4-14: Arria V GZ and Stratix V GX/GT/GS Gen1 and Gen2 Channel Placement Using the

Figure 4-15: Arria V GZ and Stratix V GX/GT/GS Gen3 Channel Placement Using the CMU and ATX PLLsGen3 requires two PLLs to facilitate rate switching be

Figure 4-16: Arria V GZ and Stratix V GX/GT/GS Gen1 and Gen2 Channel Placement Using the ATX PLLSelecting the ATX PLL has the following advantages ove

• V-Series Avalon-MM DMA Interface for PCIe Solutions User GuideRelease InformationTable 1-3: Hard IP for PCI Express Release InformationItem Descript

Test SignalsTable 4-18: Test Interface SignalsThe test_in bus provides run-time control and monitoring of the internal state of the IP core.Signal Dir

Signal Direction Descriptionhpg_ctrler[4:0]Input This signal is only available in Root Port mode and when the Slotcapability register is enabled. For

Signal Direction Descriptionpowerdown0[1:0] Output Power down <n>. This signal requests the PHY to change itspower state to the specified state

Signal Direction Description• 5’b10011: Loopback.Exit• 5’b10100: Hot.Reset• 5’b10101: L0s• 5’b11001: L2.transmit.Wake• 5’b11010: Speed.Recovery• 5’b11

Signal Direction Descriptiontxdetectrx0 Output Transmit detect receive <n>. This signal tells the PHY layer tostart a receive detection operatio

Registers52014.12.15UG-01097_sriovSubscribeSend FeedbackCorrespondence between Configuration Space Registers and the PCIeSpecificationTable 5-1: Corre

Byte Address SR-IOV Bridge Configuration Space Register Corresponding Section in PCIe Specification0x140:0x168 -ARI supported0x100:0x128 -No ARIsuppor

PCI and PCI Express Configuration Space RegistersType 0 Configuration Space RegistersFigure 5-1: Type 0 Configuration Space Registers - Byte Address O

Byte Address0x010 Base Address 0 Base Address Registers (Offset 10h -24h)0x014 Base Address 1 Base Address Registers (Offset 10h -24h)0x018 Base Addre

1. A rising edge on app_intx_req indicates the assertion of the corresponding legacy interrupt from theclient.2. In response, the PF drives Assert_INT

Example DesignsAltera provides example designs to familiarize you with the available functionality. Each design connectsthe device under test (DUT) to

MSI RegistersFigure 5-2: MSI Register Byte Address Offsets and Layout0x0500x0540x058Message ControlConfiguration MSI Control Status Register Field Des

Bits Register Description Default Value Access[16] MSI Enable. This bit must be set to enable the MSI interruptgeneration.0 RW[15:8] Next Capability P

Table 5-7: MSI Mask Register - 0x05C (32-bit addressing) or 0x060 (64-bit addressing)Bits Register Description Default Value Access31:0 Mask bits for

Bits Register Description Default Value Access[30] MSI-X Function Mask. When set, masks all MSI-X interruptsfrom this function.0RW[29:27] Reserved.0RO

Table 5-11: MSI-X Pending Bit Array (PBA) Offset Register - 0x070Bits Register Description Default Value Access[2:0] MSI-X Pending Bit Array BAR Indic

PCI Express Capability StructureFigure 5-5: PCI Express Capability Structure - Byte Address Offsets and LayoutIn the following table showing the PCI E

Bits Description Default Value Access[15] Role-Based error reporting supported 1 RO[17:16] Reserved 0 RO[27:18] Captured Slot Power Limit Value and Sc

Bits Description Default Value Access[9:4] Maximum Link Width 1, 2, 4 or 8 RO[10] ASPM Support for L0S state 0 RO[11] ASPM Support for L1 state 0 RO[1

Bits Description Default Value Access[31:5] Reserved 0 ROTable 5-19: Link Capabilities 2 Register - 0x0ACBits Description Default Value Access[0] Rese

ARI Enhanced Capability Header and Control RegisterTable 5-21: ARI Extended Capabilities RegistersAddress(hex)Name Description0x100 ARI Enhanced Capab

IP Core VerificationTo ensure compliance with the PCI Express specification, Altera performs extensive verification. Thesimulation environment uses mu

Advanced Error Reporting (AER) Enhanced Capability Header RegisterTable 5-24: AER Enhanced Capability Header Register - 0x140 (ARI supported) or 0x100

SR-IOV Virtualization Extended Capabilities RegistersFigure 5-6: SR-IOV Virtualization Extended Capabilities Registers0x1800x1840x1880x18C0x1900x1940x

Address(hex)Name Description0x190 Function Dependency Link,NumVFsThe Function Dependency field describes dependencies betweenPhysical Functions. The N

Address(hex)Name Description0x210 Lane Equalization ControlRegister 1Transmitter Preset and Receiver Preset Hint values for Lanes 2and 3 of remote dev

Bits Register Description Default Value Access[1] Reserved. Hardwired to 0. 0[2] Specifies the BAR size.: The following encodings are defined:• 1&apos

Bits Register Description Default Value Access[31:2] Reserved 0Default ValueROTable 5-30: SR-IOV Control and Status Registers - 0x188Bits Register Des

Table 5-33: VF Offset and Stride Registers - 0x194Bits Register Description Default Value Access[15:0] VF Offset. Specifies the offset of the first VF

be designated as prefetchable or non-prefetchable in Qsys. Finally, the address range of VF BAR 0 can beconfigured as any power of 2 between 128 bytes

Lane Error Status RegisterTable 5-39: Lane Error Status Register - 0x208Bits Register Description Default Value Access[7:0] Lane Error Status: Each 1

Bits Register Description Default Value Accress[31] Reserved 0 ROUncorrectable Error Status RegisterThis register controls which errors are forwarded