Altera RapidIO II MegaCore Function Bedienungsanleitung Seite 216
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Info–4 Additional Information
Document Revision History
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
June 2014,
continued
Continued on
next page
14.0
■ Modified description of
Port 0 Attributes Capture CSR
(offset 0x348, Table 6–76
on page 6–51).
■ Added new allowed value 2’b100 (Implentation specific) for
INFO_TYPE
field of This
category includes errors that do not describe a packet or control symbol, and for
which information is updated in this register but not in the
Port 0 Packet/Control
Symbol Capture 0-3
CSRs. Updated descriptions of other fields in the register to
account for the new allowed value.
■ Clarified that the value in the
ERROR_TYPE
field is based on the RapidIO big Endian
view of the bit number. Therefore, for correct correspondence with error bits in Port 0
Error Detect CSR, you must subtract the
ERROR_TYPE
value from 31.
■ Corrected Chapter 7, Testbench to state that the Altera-provided testbench does not
generate packets with
ftype
9.
■ Corrected number of TX Maintenance windows indicated in Chapter 6, Software Interface.
The IP core has two TX Maintenance windows, not 16 as was previously indicated by the
address range and name for TX Maintenance Window registers in the Extended Features
and Implementation-Defined Registers Memory Map table (Table 6–4 on page 6–4) and
in “Transmit Maintenance Registers” on page 6–35.
■ Corrected descriptions of
IDLE2 Received
bit in
LP-Serial Lane n Status 1 CSR
(Table 6–18 on page 6–23) and
CMD changed
bit in
LP-Serial Lane n Status 3 CSR
(Table 6–20 on page 6–24). Removed the corresponding fields from the description of
LP-Serial Lane n Status 2 CSR - Lane n Interrupt Enable
(Table 6–19 on
page 6–24). Neither of these two conditions triggers an interrupt.
■ Fixed assorted typos:
■ Corrected the width of the values of the
destinationID
and
sourceID
fields of the
gen_tx_data
bus in the Avalon-ST pass-through interface usage example User
Sending Read Request and Receiving Read Response to match field width.
■ Corrected width of default value for
ExtendedFeaturesPtr
field in
Assembly
Information CAR
(offset 0x0C, Table 6–25 on page 6–27).
■ Corrected default value for
LP-Serial Lane n Status 4
register bit [28]
(
Scrambling/Descrambling enabled
) (Table 6–21 on page 6–25).
■ Corrected access mode for
LP-Serial Lane n Status 4
register bit [30] (
Impl
defined
) (Table 6–21 on page 6–25).
■ Corrected bit range for
Connected port transmit emphasis Tap (-1) status
field in
LP-Serial Lane n Status 1
register (Table 6–18 on page 6–23).
■ Corrected offset for
Port 0 Link Maintenance Response
register in the Extended
Features and Implementation-Defined Registers Memory Map table (Table 6–4 on
page 6–4).
■ Corrected description of
RESPONSE_VALID
bit of
Port 0 Link Maintenance
Response CSR (offset 0x140,
Table 6–10 on page 6–9). The
link-request
control symbol is the trigger, not a fictitious link-response signal.
■ Corrected Maintenance Avalon-MM master signal names in Figure 4–17 on page 4–40
and Figure 4–19 on page 4–43.
■ In Number of Link-Request Attempts Before Declaring Fatal Error parameter
comparison in Appendix B, Differences Between RapidIO II MegaCore Function v12.1
and RapidIO MegaCore Function v12.1, corrected the name of the relevant control
symbol. Changed erroneous mention of
link-request reset-device
control
symbol to
link-request input-status
control symbol.
■ Assorted minor typos.
Date Version Changes
- User Guide 1
- RapidIO II MegaCore Function 1
- Contents 3
- Contents v 5
- Chapter 5. Signals 6
- Chapter 6. Software Interface 6
- Chapter 7. Testbench 6
- 1. About The RapidIO II 9
- MegaCore Function 9
- Releases 10
- RapidIO II IP Core Features 10
- Features 11
- Device Family Support 12
- IP Core Verification 13
- Hardware Testing 14
- Interoperability Testing 14
- Note to Table 1–3: 16
- Notes to Table 1–4: 16
- Installation and Licensing 17
- 2. Getting Started 19
- Simulating IP Cores 22
- Transceiver Settings 26
- External Transceiver PLL 26
- 3. Parameter Settings 31
- Note to Table 3–1: 32
- Enable 16-Bit Device ID Width 33
- Logical Layer Settings 34
- Capability Registers Settings 35
- Device ID 36
- Vendor ID 36
- Revision ID 36
- Assembly ID 36
- Assembly Information CAR 37
- Enable Flow Control Support 38
- Enable Switch Support 38
- Number of Ports 38
- Port Number 39
- Maximum PDU 39
- Destination Operations CAR 40
- Port General Control CSR 40
- Port 0 Control CSR 41
- Lane n Status 0 CSR 41
- Extended Features Pointer CSR 41
- 4. Functional Description 43
- Note to Table 4–2: 44
- Clocking and Reset Structure 45
- Notes to Table 4–3: 46
- RapidIO II 47
- Transactions 55
- Notes to Table 4–6: 57
- Notes to Table 4–7: 59
- Note to Table 4–8: 59
- Note to Figure 4–9: 66
- Note to Table 4–10: 70
- Notes to Table 4–11: 71
- Table 6–60 on page 6–40 72
- Note to Table 4–12: 73
- Maintenance Module 74
- Maintenance Interface Signals 75
- Doorbell Module Block Diagram 86
- Preserving Transaction Order 87
- Doorbell Module Signals 88
- Generating a Doorbell Message 88
- Receiving a Doorbell Message 89
- Transaction ID Ranges 90
- Notes to Table 4–24: 92
- Note to Table 4–26: 94
- Note to Table 4–27: 95
- field 97
- User Receiving Write Request 100
- Logical Layer Interfaces 101
- Transport Layer 112
- Receiver 113
- Transmitter 114
- Physical Layer 115
- Physical Layer Interfaces 116
- Low-level Interface Receiver 116
- CRC Checking and Removal 117
- Protocol Violations 119
- Fatal Errors 119
- Maintenance Avalon-MM Slave 120
- Maintenance Avalon-MM Master 121
- Port-Write Reception Module 122
- Input/Output Avalon-MM Slave 122
- Input/Output Avalon-MM Master 123
- 5. Signals 125
- Physical Layer Signals 126
- Low Latency Signals 127
- Multicast Event Signals 128
- Chapter 5: Signals 5–5 129
- Note to Table 5–7: 130
- Chapter 5: Signals 5–7 131
- 5–8 Chapter 5: Signals 132
- Register-Related Signals 133
- Avalon-MM Interface Signals 133
- Note to Table 5–12: 134
- Chapter 5: Signals 5–11 135
- Note to Table 5–15: 136
- Error Reporting Signals 137
- 5–14 Chapter 5: Signals 138
- 6. Software Interface 139
- Memory Map 140
- Physical Layer Registers 144
- Note to Table 6–9: 147
- Note to Table 6–14: 154
- Note to Table 6–15: 158
- Note to Table 6–17: 160
- Note to Table 6–22: 164
- Note to Table 6–23: 164
- Note to Table 6–24: 165
- Note to Table 6–25: 165
- Note to Table 6–26: 166
- Note to Table 6–27: 167
- Notes to Table 6–28: 168
- Notes to Table 6–29: 169
- Note to Table 6–30: 169
- Note to Table 6–31: 169
- Notes to Table 6–32: 170
- Note to Table 6–34: 171
- Note to Table 6–35: 171
- Note to Table 6–36: 172
- Note to Table 6–37: 172
- Transmit Port-Write Registers 174
- Receive Port-Write Registers 175
- Note to Table 6–59: 178
- Error Management Registers 180
- Note to Table 6–66: 181
- Notes to Table 6–67: 183
- Notes to Table 6–70: 185
- Notes to Table 6–71: 185
- Doorbell Message Registers 191
- Note to Table 6–89: 193
- 7. Testbench 195
- 7–2 Chapter 7: Testbench 196
- Testbench Overview 196
- Testbench Sequence 197
- 7–4 Chapter 7: Testbench 198
- Chapter 7: Testbench 7–5 199
- SWRITE Transactions 200
- NREAD Transactions 200
- NWRITE_R Transactions 201
- NWRITE Transactions 202
- Doorbell Transactions 202
- Port-Write Transactions 203
- Testbench Completion 204
- Chapter 7: Testbench 7–11 205
- 7–12 Chapter 7: Testbench 206
- A. Initialization Sequence 207
- MegaCore Function v12.1 209
- Additional Information 213
- Info–2 Additional Information 214
- Document Revision History 214
- Additional Information Info–3 215
- Info–4 Additional Information 216
- Note to Table: 217
- Info–6 Additional Information 218
- Typographic Conventions 218
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