
Altera Corporation A–29
HardCopy II Clock Uncertainty Calculator User Guide
I/O Interface
with Cascaded
PLLs
This section provides clock transfer examples for an I/O interface with
cascaded PLLs.
Figure A–30 shows an example of a clock-pair = Off-chip to CLK8
Figure A–30. Input Interface with Cascaded PLLs
Table A–30 shows input of the PLL index for Figure A–30, with respect to
the source and destination clocks.
PLL9
PLL7
INBUF
DATA
Destination
Clock
Destinatio
Register
CLK3
CLK8
Table A–30. Location of Input PLLs
Source Clock Destination Clock
1st PLL 2nd PLL 1st PLL 2nd PLL
0—97
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