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A–14 Altera Corporation

HardCopy II Clock Uncertainty Calculator User Guide

Intra-Clock Domain with Cascaded PLLs

Table A–14 shows input of the PLL index for Figure A–14, with respect to

the source and destination clocks.

1 If no PLL exists, enter “0” for both the source and destination

clocks.

Intra-Clock

Domain with

Cascaded PLLs

This section provides clock transfer examples for an intra-clock domain

with cascaded PLLs.

Figure A–15 shows an example of a clock-pair = CLK7 to CLK7

Figure A–15. Intra-Clock Domain with Cascaded PLLs and Shared PLL Output

Table A–15 shows input of the PLL index for Figure A–15, with respect to

the source and destination clocks.

Table A–14. Location of Input PLLs

Source Clock Destination Clock

1st PLL 2nd PLL 1st PLL 2nd PLL

0—0—

INBUF

PLL5

PLL4

CLK7

Source

Clock

Destination

Clock

Source

Regist

Destination

CLK3

Table A–15. Location of Input PLLs

Source Clock Destination Clock

1st PLL 2nd PLL 1st PLL 2nd PLL

5454

1 2 ... 41 42 43 44 45 46 47 48 49 50 51 ... 61 62

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Altera HardCopy II Clock Uncertainty Calculator Bedienungsanleitung Seite 46