Altera Triple Speed Ethernet MegaCore Function Bedienungsanleitung Seite 86
- Seite / 223
- Inhaltsverzeichnis
- LESEZEICHEN
Bewertet. / 5. Basierend auf Kundenbewertungen
Base Configuration Registers (Dword Offset 0x00 – 0x17)
Table 6-2 lists the base registers you can use to configure the MAC function. A software reset does not reset
these registers except the first two bits (TX_ENA and RX_ENA = 0) in the command_config register.
Table 6-2: Base Configuration Register Map
HW ResetDescriptionR/WNameDword
Offset
<IP
version
number>
• Bits[15:0]—Set to the current version of the MegaCore
function.
• Bits[31:16]—Customer specific revision, specified by
the CUST_VERSION parameter defined in the top-level
file generated for the instance of the MegaCore
function. These bits are set to 0 during the configura-
tion of the MegaCore function.
ROrev0x00
0Scratch register. Provides a memory location for you to
test the device memory operation.
RWscratch(1)0x01
0MAC configuration register. Use this register to control
and configure the MAC function. The MAC function
starts operation as soon as the transmit and receive enable
bits in this register are turned on. Altera, therefore,
recommends that you configure this register last.
See Command_Config Register (Dword Offset 0x02)
on page 6-7 for the bit description.
RWcommand_config0x02
06-byte MAC primary address. The first four most
significant bytes of the MAC address occupy mac_0 in
reverse order. The last two bytes of the MAC address
occupy the two least significant bytes of mac_1 in reverse
order.
For example, if the MAC address is 00-1C-23-17-4A-CB,
the following assignments are made:
mac_0 = 0x17231c00
mac_1 = 0x0000CB4a
Ensure that you configure these registers with a valid
MAC address if you disable the promiscuous mode
(PROMIS_EN bit in command_config = 0).
RWmac_00x03
0RWmac_10x04
1518• Bits[15:0]—16-bit maximum frame length in bytes.
The MegaCore function checks the length of receive
frames against this value. Typical value is 1518.
In 10/100 and 1000 Small MAC core variations, this
register is RO and the maximum frame length is fixed
to 1518.
• Bits[31:16]—unused.
RW/
RO
frm_length0x05
Altera Corporation
Configuration Register Space
Send Feedback
6-3
Base Configuration Registers (Dword Offset 0x00 – 0x17)
UG-01008
2014.06.30
- User Guide 1
- Contents 2
- Altera Corporation 10
- About This MegaCore Function 10
- Send Feedback 10
- High-Level Block Diagrams 10
- Figure 1-2: Multi-port MAC 11
- 10/100/1000-Mbps 12
- Ethernet MAC 12
- Optical Platform 14
- Copper Platform 14
- Release Information 18
- DescriptionItem 19
- Using the Parameter Editor 24
- Design Walkthrough 25
- Simulate the System 27
- Programming an FPGA Device 27
- Generated Files 28
- DescriptionFile Name 29
- Quartus II Pin 29
- Assignment 29
- Parameter Settings 30
- Ethernet MAC Options 31
- FIFO Options 33
- Timestamp Options 34
- PCS/Transceiver Options 34
- ParameterValueName 35
- Functional Description 37
- MAC Architecture 38
- MAC Interfaces 39
- MAC Transmit Datapath 40
- IP Payload Re-alignment 41
- Address Insertion 41
- Frame Payload Padding 41
- CRC-32 Generation 41
- Interpacket Gap Insertion 42
- MAC Receive Datapath 43
- ValueHash Code Bit 44
- Frame Type Validation 45
- Payload Pad Removal 46
- CRC Checking 46
- Length Checking 46
- Frame Writing 47
- IP Payload Alignment 47
- FIFO Buffer Thresholds 48
- Receive Thresholds 49
- Transmit Thresholds 51
- Congestion and Flow Control 52
- Magic Packets 53
- MAC Local Loopback 54
- MAC Error Correction Code 55
- MAC Reset 55
- PHY Management (MDIO) 56
- MDIO Connection 57
- MDIO Frame Format 57
- Gigabit Ethernet 58
- Programmable 10/100 Ethernet 59
- Transmit Operation 62
- Receive Operation 63
- SGMII Converter 64
- Auto-Negotiation 65
- SGMII Auto-Negotiation 66
- Ten-bit Interface 68
- PHY Loopback 69
- PHY Power-Down 69
- POWERDOWN 70
- 1000BASE-X PCS 70
- IEEE 1588v2 Features 72
- Time of Day 73
- IEEE 1588v2 Receive Datapath 74
- IEEE 1588v2 Frame Format 74
- 0..1500/9600 Octets 75
- 4 Octets 75
- CRC4 Octets 76
- 0..1500/9600 Octets Payload 76
- MAC Header 77
- UDP Header 77
- IP Header 77
- PTP Header 77
- Software Requirements 78
- Base Addresses 80
- IEEE 1588v2 Feature PMA Delay 100
- UG-01008 101
- 2014.06.30 101
- DescriptionR/WNameBit(s) 103
- DescriptionR/WNameBit 105
- 1000BASE-X 106
- Register Initialization 110
- Configuration Register Space 111
- Interface Signals 116
- Clock and Reset Signal 117
- MAC Control Interface Signals 118
- MAC Status Signals 118
- MAC Receive Interface Signals 119
- DescriptionBit 120
- DescriptionI/OName 123
- MII/GMII/RGMII Signals 124
- PHY Management Signals 125
- ECC Status Signals 126
- TBI Interface Signals 131
- Status LED Control Signals 132
- SERDES Control Signals 132
- Related Information 133
- SectionInterface Signal 135
- 1.25 Gbps Serial Interface 138
- Transceiver Native PHY Signal 138
- DescriptionWidthI/OSignal 141
- 1000BASE-X/SGMII PCS Signals 149
- PCS Control Interface Signals 150
- PCS Reset Signals 150
- SGMII Status Signals 152
- Avalon-ST Receive Interface 155
- IEEE 1588v2 Timestamp 162
- Design Considerations 163
- Configurations(1) 164
- Sharing Transceiver Quads 169
- Timing Constraints 171
- Recommended Clock Frequency 173
- 50–100CLK 174
- 1000BASE-X/SGMII PCS only 174
- 125REF_CLK 174
- 125TBI_TX_CLK 174
- 125TBI_RX_CLK 174
- Testbench 175
- Testbench Verification 176
- Testbench Configuration 177
- Test Flow 177
- Simulation Model 178
- Simulation Model Files 179
- Driver Architecture 180
- PHY Speed Bits 181
- Speed (Mbps) 181
- Using Jumbo Frames 183
- API Functions 184
- Constants 189
- DescriptionValueConstant 190
- Ethernet Frame Format 192
- Pause Frame Format 194
- Description 195
- XON_GENXOFF_GEN 195
- Simulation Parameters 196
- DefaultDescriptionParameter 197
- Test Configuration Parameters 198
- Time-of-Day (ToD) Clock 201
- ToD Clock Parameter Setting 202
- ToD Clock 203
- DescriptionR/WNameDword 205
- Adjusting ToD Clock Drift 206
- ToD Synchronizer 207
- ToD Synchronizer Block 208
- 32/6364/31516/6364/63Settings 209
- DescriptionValueName 209
- ToD Synchronizer Signals 210
- Packet Classifier 212
- Packet Classifier Signals 213
- Additional Information 217
- Document Revision History 218
- ChangesVersionDate 219
- How to Contact Altera 223
Verwandte Produkte und Handbücher für Messgeräte Altera Triple Speed Ethernet MegaCore Function
Messgeräte Altera OCT Bedienungsanleitung
(10 Seiten)
(10 Seiten)
Messgeräte Altera Embedded Systems Development Kit, Cyclone III Edit Bedienungsanleitung
(82 Seiten)
(82 Seiten)
Messgeräte Altera PHYLite Bedienungsanleitung
(61 Seiten)
(61 Seiten)
Messgeräte Altera Arria GX Bedienungsanleitung
(32 Seiten)
(32 Seiten)
Messgeräte Altera Arria V GX Bedienungsanleitung
(52 Seiten)
(52 Seiten)
© 2020, manymanuals.de. Alle Rechte vorbehalten. | 0.070 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Kommentare zu diesen Handbüchern