Altera Triple Speed Ethernet MegaCore Function Bedienungsanleitung Seite 46
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Payload Pad Removal
You can turn on padding removal by setting the PAD_EN bit in the command_config register to 1. The MAC
function removes the padding, prior to forwarding the frames to the user application, when the payload
length is less than the following values for the different frame types:
• 46 bytes for basic MAC frames
• 42 bytes for VLAN tagged frames
• 38 bytes for stacked VLAN tagged frames
When padding removal is turned off, complete frames including the padding are forwarded to the Avalon-
ST receive interface.
CRC Checking
The following equation shows the CRC polynomial, as specified in the IEEE 802.3 standard:
FCS(X) = X
32
+X
26
+X
23
+X
22
+X
16
+X
12
+X
11
+X
10
+X
8
+X
7
+X
5
+X
4
+X
2
+X
1
+1
The 32-bit CRC value occupies the FCS field with X31 in the least significant bit of the first byte. The CRC
bits are thus received in the following order: X31, X30,..., X1, X0.
If the MAC function detects CRC-32 error, it marks the frame invalid by asserting the following signals:
• rx_err[2] in MAC variations with internal FIFO buffers.
• data_rx_error[1] in MAC variations without internal FIFO buffers.
The MAC function discards frames with CRC-32 error if the RX_ERR_DISC bit in the command_config register
is set to 1.
The MAC function forwards the CRC-32 field to the user application if the CRC_FWD and PAD_EN bits in the
command_config register are 1 and 0 respectively. Otherwise, the CRC-32 field is removed from the frame.
Length Checking
The MAC function checks the frame and payload lengths of basic, VLAN tagged, and stacked VLAN tagged
frames.
The frame length must be at least 64 (0x40) bytes and not exceed the following maximum value for the
different frame types:
• Basic frames—the value specified in the frm_length register
• VLAN tagged frames—the value specified in the frm_length register plus four
• Stacked VLAN tagged frames—the value specified in the frm_length register plus eight
To prevent FIFO buffer overflow, the MAC function truncates the frame if it is more than 11 bytes longer
than the allowed maximum length.
For frames of a valid length, the MAC function continues to check the payload length if the NO_LGTH_CHECK
bit in the command_config register is set to 0. The MAC function keeps track of the payload length as it
receives a frame, and checks the length against the length/type field in basic MAC frames or the client
length/type field in VLAN tagged frames. The payload length is valid if it satisfies the following conditions:
• The actual payload length matches the value in the length/type or client length/type field.
• Basic frames—the payload length is between 46 (0x2E)and 1536 (0x0600) bytes, excluding 1536.
• VLAN tagged frames—the payload length is between 42 (0x2A)and 1536 (0x0600), excluding 1536.
Functional Description
Altera Corporation
Send Feedback
UG-01008
Payload Pad Removal
4-10
2014.06.30
- User Guide 1
- Contents 2
- Altera Corporation 10
- About This MegaCore Function 10
- Send Feedback 10
- High-Level Block Diagrams 10
- Figure 1-2: Multi-port MAC 11
- 10/100/1000-Mbps 12
- Ethernet MAC 12
- Optical Platform 14
- Copper Platform 14
- Release Information 18
- DescriptionItem 19
- Using the Parameter Editor 24
- Design Walkthrough 25
- Simulate the System 27
- Programming an FPGA Device 27
- Generated Files 28
- DescriptionFile Name 29
- Quartus II Pin 29
- Assignment 29
- Parameter Settings 30
- Ethernet MAC Options 31
- FIFO Options 33
- Timestamp Options 34
- PCS/Transceiver Options 34
- ParameterValueName 35
- Functional Description 37
- MAC Architecture 38
- MAC Interfaces 39
- MAC Transmit Datapath 40
- IP Payload Re-alignment 41
- Address Insertion 41
- Frame Payload Padding 41
- CRC-32 Generation 41
- Interpacket Gap Insertion 42
- MAC Receive Datapath 43
- ValueHash Code Bit 44
- Frame Type Validation 45
- Payload Pad Removal 46
- CRC Checking 46
- Length Checking 46
- Frame Writing 47
- IP Payload Alignment 47
- FIFO Buffer Thresholds 48
- Receive Thresholds 49
- Transmit Thresholds 51
- Congestion and Flow Control 52
- Magic Packets 53
- MAC Local Loopback 54
- MAC Error Correction Code 55
- MAC Reset 55
- PHY Management (MDIO) 56
- MDIO Connection 57
- MDIO Frame Format 57
- Gigabit Ethernet 58
- Programmable 10/100 Ethernet 59
- Transmit Operation 62
- Receive Operation 63
- SGMII Converter 64
- Auto-Negotiation 65
- SGMII Auto-Negotiation 66
- Ten-bit Interface 68
- PHY Loopback 69
- PHY Power-Down 69
- POWERDOWN 70
- 1000BASE-X PCS 70
- IEEE 1588v2 Features 72
- Time of Day 73
- IEEE 1588v2 Receive Datapath 74
- IEEE 1588v2 Frame Format 74
- 0..1500/9600 Octets 75
- 4 Octets 75
- CRC4 Octets 76
- 0..1500/9600 Octets Payload 76
- MAC Header 77
- UDP Header 77
- IP Header 77
- PTP Header 77
- Software Requirements 78
- Base Addresses 80
- IEEE 1588v2 Feature PMA Delay 100
- UG-01008 101
- 2014.06.30 101
- DescriptionR/WNameBit(s) 103
- DescriptionR/WNameBit 105
- 1000BASE-X 106
- Register Initialization 110
- Configuration Register Space 111
- Interface Signals 116
- Clock and Reset Signal 117
- MAC Control Interface Signals 118
- MAC Status Signals 118
- MAC Receive Interface Signals 119
- DescriptionBit 120
- DescriptionI/OName 123
- MII/GMII/RGMII Signals 124
- PHY Management Signals 125
- ECC Status Signals 126
- TBI Interface Signals 131
- Status LED Control Signals 132
- SERDES Control Signals 132
- Related Information 133
- SectionInterface Signal 135
- 1.25 Gbps Serial Interface 138
- Transceiver Native PHY Signal 138
- DescriptionWidthI/OSignal 141
- 1000BASE-X/SGMII PCS Signals 149
- PCS Control Interface Signals 150
- PCS Reset Signals 150
- SGMII Status Signals 152
- Avalon-ST Receive Interface 155
- IEEE 1588v2 Timestamp 162
- Design Considerations 163
- Configurations(1) 164
- Sharing Transceiver Quads 169
- Timing Constraints 171
- Recommended Clock Frequency 173
- 50–100CLK 174
- 1000BASE-X/SGMII PCS only 174
- 125REF_CLK 174
- 125TBI_TX_CLK 174
- 125TBI_RX_CLK 174
- Testbench 175
- Testbench Verification 176
- Testbench Configuration 177
- Test Flow 177
- Simulation Model 178
- Simulation Model Files 179
- Driver Architecture 180
- PHY Speed Bits 181
- Speed (Mbps) 181
- Using Jumbo Frames 183
- API Functions 184
- Constants 189
- DescriptionValueConstant 190
- Ethernet Frame Format 192
- Pause Frame Format 194
- Description 195
- XON_GENXOFF_GEN 195
- Simulation Parameters 196
- DefaultDescriptionParameter 197
- Test Configuration Parameters 198
- Time-of-Day (ToD) Clock 201
- ToD Clock Parameter Setting 202
- ToD Clock 203
- DescriptionR/WNameDword 205
- Adjusting ToD Clock Drift 206
- ToD Synchronizer 207
- ToD Synchronizer Block 208
- 32/6364/31516/6364/63Settings 209
- DescriptionValueName 209
- ToD Synchronizer Signals 210
- Packet Classifier 212
- Packet Classifier Signals 213
- Additional Information 217
- Document Revision History 218
- ChangesVersionDate 219
- How to Contact Altera 223
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