Altera Triple Speed Ethernet MegaCore Function Bedienungsanleitung PDF herunterladen (Seite 150)

PCS Control Interface Signals

Table 7-36: Register Interface Signals

DescriptionI/OAvalon-MM Signal

Type

Name

value less than or equal to 125-MHz.

Iclkreg_clk

Active-high reset signal for reg_clk clock domain.Iresetreset_reg_clk

16-bit word-aligned register address.Iaddressreg_addr[4:0]

or register write. A value of 0 indicates that the read

or write is complete.

Owaitrequestreg_busy

PCS Reset Signals

Table 7-37: Reset Signals

DescriptionI/OName

Active-high reset signal for PCS rx_clk clock domain. Assert this

signal to reset the logic synchronized by rx_clk.

Ireset_rx_clk

Active-high reset signal for PCS tx_clk clock domain. Assert this

signal to reset the logic synchronized by tx_clk.

Ireset_tx_clk

MII/GMII Clocks and Clock Enablers

Data transfers on the MII/GMII interface are synchronous to the receive and transmit clocks.

Table 7-38: MAC Clock Signals

DescriptionI/OName

Receive clock. This clock is derived from the TBI clock tbi_rx_clk

and set to 125 MHz.

Orx_clk

Transmit clock. This clock is derived from the TBI clock tbi_tx_clk

and set to 125 MHz.

Otx_clk

Receive clock enabler. In SGMII mode, this signal enables rx_clk.Orx_clkena

Transmit clock enabler. In SGMII mode, this signal enables tx_clk.Otx_clkena

Altera Corporation

Interface Signals

Send Feedback

7-35

PCS Control Interface Signals

UG-01008

2014.06.30

1 2 ... 145 146 147 148 149 150 151 152 153 154 155 ... 222 223

Keine Kommentare

Altera Triple Speed Ethernet MegaCore Function Bedienungsanleitung Seite 150