Altera Triple Speed Ethernet MegaCore Function Bedienungsanleitung PDF herunterladen (Seite 48)

Table 4-5: Transmit and Receive Nominal Latency

The transmit and receive nominal latencies in various modes. The FIFO buffer thresholds are set to the typical values

specified in this user guide when deriving the latencies.

Latency (Clock Cycles) (1)

MAC Configuration

ReceiveTransmit

MAC with Internal FIFO Buffers (2)

11032GMII in cut-through mode

21841MII in cut-through mode

11333RGMII in gigabit and cut-through mode

22142RGMII in 10/100 Mbps and cut-through mode

MAC without Internal FIFO Buffers (3)

3711GMII

7722MII

4012RGMII in gigabit mode

8023RGMII in10/100 Mbps

Notes to Table 4-5 :

1. The clocks in all domains are running at the same frequency.

2. The data width is set to 32 bits.

3. The data width is set to 8 bits.

Related Information

Base Configuration Registers (Dword Offset 0x00 – 0x17) on page 6-3

FIFO Buffer Thresholds

For MAC variations with internal FIFO buffers, you can change the operations of the FIFO buffers, and

manage potential FIFO buffer overflow or underflow by configuring the following thresholds:

• Almost empty

• Almost full

• Section empty

• Section full

These thresholds are defined in bytes for 8-bit wide FIFO buffers and in words for 32-bit wide FIFO buffers.

The FIFO buffer thresholds are configured via the registers.

Functional Description

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FIFO Buffer Thresholds

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2014.06.30

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Altera Triple Speed Ethernet MegaCore Function Bedienungsanleitung Seite 48