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SystemVerilog Master BFM
Master BFM Configuration
Mentor Verification IP AE AXI4-Lite User Guide, V10.3
41
April 2014
A master BFM has configuration fields that you can set with the set_config() function to
configure timeout factors, and setup and hold times, and so on. You can also get the value of a
configuration field using the get_config() function. Table 3-2 describes the full list of
configuration fields.
WRITE_ISSUING_
CAPABILITY
The maximum number of outstanding write transactions that
can be issued from the master BFM. This parameter is set
with the Qsys Parameter Editor. See “Running the Qsys
Tool” on page 356. for details.
Default: 16.
COMBINED_ISSUING_
CAPABILITY
The maximum number of outstanding combined read and
write transactions that can be issued from the master BFM.
This parameter is set with the Qsys Parameter Editor. See
“Running the Qsys Tool” on page 356. for details.
Default: 16.
Table 3-2. Master BFM Configuration
Configuration Field Description
Timing Variables
AXI4_CONFIG_SETUP_TIME The setup-time prior to the active edge
of ACLK, in units of simulator time-
steps for all signals.1 Default: 0.
AXI4_CONFIG_HOLD_TIME The hold-time after the active edge of
ACLK, in units of simulator time-steps
for all signals.1 Default: 0.
AXI4_CONFIG_MAX_TRANSACTION_TIME_
FACTOR
The maximum timeout duration for a
read/write transaction in clock cycles.
Default: 100000.
AXI4_CONFIG_BURST_TIMEOUT_FACTOR The maximum delay between the
individual phases of a read/write
transaction in clock cycles. Default:
10000.
AXI4_CONFIG_MAX_LATENCY_AWVALID_
ASSERTION_TO_AWREADY
The maximum timeout duration from
the assertion of AWVALID to the
assertion of AWREADY in clock
periods. Default: 1000.
AXI4_CONFIG_MAX_LATENCY_ARVALID_
ASSERTION_TO_ARREADY
The maximum timeout duration from
the assertion of ARVALID to the
assertion of ARREADY in clock
periods. Default: 10000.
Table 3-1. Master BFM Signal Width Parameters (cont.)
Signal Width Parameter Description
- AMBA AXI4-Lite 1
- User Guide 1
- Table of Contents 10
- List of Examples 12
- List of Figures 14
- List of Tables 15
- About This User Guide 17
- Protocol Restrictions 17
- Supported Simulators 18
- Simulator GCC Requirements 18
- Chapter 1 21
- Mentor VIP Altera Edition 21
- What Is a Transaction? 22
- AXI4-Lite Transactions 22
- Chapter 2 27
- SystemVerilog API Overview 27
- Chapter 3 39
- SystemVerilog Master BFM 39
- SystemVerilog Master API 43
- Returns 44
- Example 58
- Chapter 4 63
- SystemVerilog Slave BFM 63
- SystemVerilog Slave API 68
- Arguments config_name 69
- Chapter 5 91
- SystemVerilog Monitor API 96
- Prototype 100
- Arguments 100
- April 2014 102
- SystemVerilog Monitor BFM 105
- Helper Functions 111
- SystemVerilog Tutorials 115
- Chapter 6 115
- BFM Master Test Program 116
- Verifying a Slave DUT 117
- Verifying a Master DUT 123
- Basic Slave API Definition 124
- *_valid_delay = 4 127
- *_ready_delay = 2 127
- Advanced Slave API Definition 129
- Initial Block 131
- Chapter 7 137
- VHDL API Overview 137
- Test Program VHDL 138
- Configuration 139
- Creating Transactions 139
- Transaction Definition 140
- Executing Transactions 144
- Waiting Events 145
- Access Transaction Record 146
- Operation Mode 147
- Channel Handshake Delay 147
- Handshake Delay 148
- Transaction Done 149
- Chapter 8 151
- VHDL Master BFM 151
- Master BFM Protocol Support 152
- Master Timing and Events 152
- Master BFM Configuration 152
- Master Assertions 155
- VHDL Master API 156
- Chapter 9 213
- VHDL Slave BFM 213
- Slave BFM Configuration 214
- Slave Assertions 216
- VHDL Slave API 217
- Operational 223
- Transaction 223
- Chapter 10 279
- VHDL Monitor BFM 279
- Monitor BFM Configuration 280
- Monitor Assertions 282
- VHDL Monitor API 283
- Chapter 11 335
- VHDL Tutorials 335
- BFM Slave Test Program 341
- Chapter 12 353
- Running the Qsys Tool 356
- Running a Simulation 359
- ModelSim Simulation 360
- Editing the modelsim.ini File 363
- Questa Simulation 364
- Cadence IES Simulation 364
- Synopsys VCS Simulation 366
- Appendix A 369
- AXI4-Lite Assertions 384
- Appendix B 385
- SystemVerilog Test Programs 385
- Appendix C 397
- VHDL Test Programs 397
- End-User License Agreement 409
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