Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Bedienungsanleitung PDF herunterladen (Seite 124)

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Mentor Verification IP AE AXI4-Lite User Guide, V10.3

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SystemVerilog Tutorials

Verifying a Master DUT

April 2014

For a complete code listing of the slave test program, refer to “SystemVerilog AXI4-Lite Slave

BFM Test Program” on page 390.

Basic Slave API Definition

The Basic Slave Test Program API contains the following elements:

• Functions that read and write a byte of data to Internal Memory include do_byte_read()

and do_byte_write(), respectively.

• Functions set_read_data_valid_delay() and set_wr_resp_valid_delay() to configure the

delay of the read data channel RVALID, and write response channel BVALID signals,

respectively.

• Variables m_rd_addr_phase_ready_delay and m_wr_addr_phase_ready_delay to

configure the delay of the read/write address channel ARVALID/AWVALID signals,

and m_wr_data_phase_ready_delay to configure the delay of the write response channel

BVALID signal.

• A slave_ready_delay_mode variable to configure the behavior of the handshake signals

*VALID to *READY delay.

Internal Memory

The internal memory for the slave is defined as a sparse array of 8 bits, so that each byte of data

is stored as an address/data pair.

Example 6-8. Internal Memory

// Storage for a memory

bit [7:0] mem [*];

do_byte_read()

The do_byte_read() function, when called, will read a data byte from the Internal Memory mem,

given an address location as shown below.

You can edit this function to modify the way the read data is extracted from the internal

memory.

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