Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Bedienungsanleitung Seite 369
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Mentor Verification IP AE AXI4-Lite User Guide, V10.3
369
April 2014
Appendix A
AXI4-Lite Assertions
The AXI4-Lite master, slave, and monitor BFMs all support error checking with the firing of
one or more assertions when a property defined in the AMBA AXI Protocol Specification has
been violated. Each assertion can be individually enabled/disabled using the set_config()
function for a particular BFM. The property covered for each assertion is noted in under the
Property Reference column. The reference number refers to the section number in the AMBA
AXI Protocol Specification.
Note
The AXI4-Lite BFM assertions cover the full AXI4 protocol.
Table A-1. AXI4 Assertions
Error
Code
Error Name Description Property
Ref
AXI4-
60000
AXI4_ADDRESS_WIDTH_EXCEEDS_64 AXI4 supports up to 64-bit
addressing.
A10.3.1
AXI4-
60001
AXI4_ADDR_FOR_READ_BURST_
ACROSS_4K_BOUNDARY
This read transaction has crossed a
4KB boundary.
A3.4.1
AXI4-
60002
AXI4_ADDR_FOR_WRITE_BURST_
ACROSS_4K_BOUNDARY
This write transaction has crossed a
4KB boundary.
A3.4.1
AXI4-
60003
AXI4_ARADDR_CHANGED_BEFORE_
ARREADY
The value of ARADDR has changed
from its initial value between the time
ARVALID was asserted and before
ARREADY was asserted.
A3.2.1
AXI4-
60004
AXI4_ARADDR_FALLS_IN_REGION_
HOLE
The ARADDR value cannot be
decoded to a region in the region
map.
A8.2.1
AXI4-
60005
AXI4_ARADDR_UNKN ARADDR has an X value/ARADDR
has a Z value.
AXI4-
60006
AXI4_ARBURST_CHANGED_BEFORE_
ARREADY
The value of ARBURST has
changed from its initial value
between the time ARVALID was
asserted and before ARREADY was
asserted.
A3.2.1
AXI4-
60007
AXI4_ARBURST_UNKN ARBURST has an X
value/ARBURST has a Z value.
- AMBA AXI4-Lite 1
- User Guide 1
- Table of Contents 10
- List of Examples 12
- List of Figures 14
- List of Tables 15
- About This User Guide 17
- Protocol Restrictions 17
- Supported Simulators 18
- Simulator GCC Requirements 18
- Chapter 1 21
- Mentor VIP Altera Edition 21
- What Is a Transaction? 22
- AXI4-Lite Transactions 22
- Chapter 2 27
- SystemVerilog API Overview 27
- Chapter 3 39
- SystemVerilog Master BFM 39
- SystemVerilog Master API 43
- Returns 44
- Example 58
- Chapter 4 63
- SystemVerilog Slave BFM 63
- SystemVerilog Slave API 68
- Arguments config_name 69
- Chapter 5 91
- SystemVerilog Monitor API 96
- Prototype 100
- Arguments 100
- April 2014 102
- SystemVerilog Monitor BFM 105
- Helper Functions 111
- SystemVerilog Tutorials 115
- Chapter 6 115
- BFM Master Test Program 116
- Verifying a Slave DUT 117
- Verifying a Master DUT 123
- Basic Slave API Definition 124
- *_valid_delay = 4 127
- *_ready_delay = 2 127
- Advanced Slave API Definition 129
- Initial Block 131
- Chapter 7 137
- VHDL API Overview 137
- Test Program VHDL 138
- Configuration 139
- Creating Transactions 139
- Transaction Definition 140
- Executing Transactions 144
- Waiting Events 145
- Access Transaction Record 146
- Operation Mode 147
- Channel Handshake Delay 147
- Handshake Delay 148
- Transaction Done 149
- Chapter 8 151
- VHDL Master BFM 151
- Master BFM Protocol Support 152
- Master Timing and Events 152
- Master BFM Configuration 152
- Master Assertions 155
- VHDL Master API 156
- Chapter 9 213
- VHDL Slave BFM 213
- Slave BFM Configuration 214
- Slave Assertions 216
- VHDL Slave API 217
- Operational 223
- Transaction 223
- Chapter 10 279
- VHDL Monitor BFM 279
- Monitor BFM Configuration 280
- Monitor Assertions 282
- VHDL Monitor API 283
- Chapter 11 335
- VHDL Tutorials 335
- BFM Slave Test Program 341
- Chapter 12 353
- Running the Qsys Tool 356
- Running a Simulation 359
- ModelSim Simulation 360
- Editing the modelsim.ini File 363
- Questa Simulation 364
- Cadence IES Simulation 364
- Synopsys VCS Simulation 366
- Appendix A 369
- AXI4-Lite Assertions 384
- Appendix B 385
- SystemVerilog Test Programs 385
- Appendix C 397
- VHDL Test Programs 397
- End-User License Agreement 409
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