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Mentor Verification IP AE AXI4-Lite User Guide, V10.3
192
VHDL Master BFM
execute_transaction()
April 2014
execute_transaction()
This procedure executes a master transaction that is uniquely identified by the transaction_id
argument, previously created with either the create_write_transaction() or procedure. A
transaction can be blocking (default) or nonblocking, based on the setting of the transaction
operation_mode field.
The results of execute_transaction() for write transactions varies based on how write transaction
fields are set. If the transaction gen_write_strobes field is set, execute_transaction ()
automatically corrects any previously set write_strobes field array elements. However, if the
gen_write_strobes field is not set, then any previously assigned write_strobes field array
elements will be passed onto the WSTRB protocol signals, which can result in a protocol
violation if not correctly set. Refer to “Automatic Correction of Byte Lane Strobes” on page 146
for more details.
If the write_data_mode field for a write transaction is set to AXI4_DATA_WITH_ADDRESS,
execute_transaction () calls the execute_write_addr_phase() and execute_write_data_phase()
procedures simultaneously; otherwise, execute_write_data_phase() is called after
execute_write_addr_phase() so that the write data beat occurs after the write address phase
(default). It then calls the get_write_response_phase() procedure to complete the write
transaction.
For a read transaction, execute_transaction() calls the execute_read_addr_phase() procedure
followed by the get_read_data_phase() procedure to complete the read transaction
Prototype
procedure execute_transaction
(
transaction_id : in integer;
bfm_id : in integer;
path_id : in axi4_path_t; --optional
signal tr_if : inout axi4_vhd_if_struct_t
);
Arguments transaction_id
Transaction identifier. Refer to “Overloaded Procedure
Common Arguments” on page 151 for more details.
bfm_id BFM identifier. Refer to “Overloaded Procedure
Common Arguments” on page 151 for more details.
path_id (Optional) Parallel process path identifier:
AXI4_PATH_0
AXI4_PATH_1
AXI4_PATH_2
AXI4_PATH_3
AXI4_PATH_4
Refer to “Overloaded Procedure Common Arguments”
on page 151 for more details.
tr_if Transaction signal interface. Refer to “Overloaded
Procedure Common Arguments” on page 151 for more
details.
Returns
None
- AMBA AXI4-Lite 1
- User Guide 1
- Table of Contents 10
- List of Examples 12
- List of Figures 14
- List of Tables 15
- About This User Guide 17
- Protocol Restrictions 17
- Supported Simulators 18
- Simulator GCC Requirements 18
- Chapter 1 21
- Mentor VIP Altera Edition 21
- What Is a Transaction? 22
- AXI4-Lite Transactions 22
- Chapter 2 27
- SystemVerilog API Overview 27
- Chapter 3 39
- SystemVerilog Master BFM 39
- SystemVerilog Master API 43
- Returns 44
- Example 58
- Chapter 4 63
- SystemVerilog Slave BFM 63
- SystemVerilog Slave API 68
- Arguments config_name 69
- Chapter 5 91
- SystemVerilog Monitor API 96
- Prototype 100
- Arguments 100
- April 2014 102
- SystemVerilog Monitor BFM 105
- Helper Functions 111
- SystemVerilog Tutorials 115
- Chapter 6 115
- BFM Master Test Program 116
- Verifying a Slave DUT 117
- Verifying a Master DUT 123
- Basic Slave API Definition 124
- *_valid_delay = 4 127
- *_ready_delay = 2 127
- Advanced Slave API Definition 129
- Initial Block 131
- Chapter 7 137
- VHDL API Overview 137
- Test Program VHDL 138
- Configuration 139
- Creating Transactions 139
- Transaction Definition 140
- Executing Transactions 144
- Waiting Events 145
- Access Transaction Record 146
- Operation Mode 147
- Channel Handshake Delay 147
- Handshake Delay 148
- Transaction Done 149
- Chapter 8 151
- VHDL Master BFM 151
- Master BFM Protocol Support 152
- Master Timing and Events 152
- Master BFM Configuration 152
- Master Assertions 155
- VHDL Master API 156
- Chapter 9 213
- VHDL Slave BFM 213
- Slave BFM Configuration 214
- Slave Assertions 216
- VHDL Slave API 217
- Operational 223
- Transaction 223
- Chapter 10 279
- VHDL Monitor BFM 279
- Monitor BFM Configuration 280
- Monitor Assertions 282
- VHDL Monitor API 283
- Chapter 11 335
- VHDL Tutorials 335
- BFM Slave Test Program 341
- Chapter 12 353
- Running the Qsys Tool 356
- Running a Simulation 359
- ModelSim Simulation 360
- Editing the modelsim.ini File 363
- Questa Simulation 364
- Cadence IES Simulation 364
- Synopsys VCS Simulation 366
- Appendix A 369
- AXI4-Lite Assertions 384
- Appendix B 385
- SystemVerilog Test Programs 385
- Appendix C 397
- VHDL Test Programs 397
- End-User License Agreement 409
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