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VHDL API Overview
Waiting Events
Mentor Verification IP AE AXI4-Lite User Guide, V10.3
145
April 2014
Waiting Events
Each BFM API has procedures that block the test program code execution until an event has
occurred.
The wait_on() procedure blocks the test program until an ACLK or ARESETn signal event has
occurred before proceeding.
The get*_transaction(), get*_phase(), get*_cycle() procedures block the test program code
execution until a complete transaction, phase or cycle has occurred, respectively.
wait_on()
For example, a BFM test program can wait for the positive edge of the ARESETn signal using
the following code:
-- Block test program execution until the positive edge of the clock
wait_on(AXI4_RESET_POSEDGE, bfm_index, axi4_tr_if_0(bfm_index));
In the above example, the bfm_index specifies the BFM.
get*_transaction(), get*_phase(), get*_cycle()
For example, a slave BFM test program can use a received write address phase to form the
response of the write transaction. The test program gets the write address phase for the
transaction by calling the get_write_addr_phase() procedure. This task blocks until it has
received the address phase, allowing the test program to then call the
execute_write_response_phase() procedure for the transaction, as shown in the slave BFM test
program in Example 7-2 below.
Example 7-2. Slave BFM Test Program Using get_write_addr_phase()
create_slave_transaction(write_trans, bfm_index, axi4_tr_if_0(bfm_index));
get_write_addr_phase(write_trans, bfm_index, axi4_tr_if_0(bfm_index));
...
execute_write_response_phase(write_trans, bfm_index, AXI4_PATH_2,
axi4_tr_if_2(bfm_index));
In the above example, the bfm_index specifies the BFM.
Note
Not all BFM APIs support the full complement of get*_transaction(), get*_phase(),
get*_cycle() tasks. Refer to the individual master, slave, or monitor BFM API for details.
- AMBA AXI4-Lite 1
- User Guide 1
- Table of Contents 10
- List of Examples 12
- List of Figures 14
- List of Tables 15
- About This User Guide 17
- Protocol Restrictions 17
- Supported Simulators 18
- Simulator GCC Requirements 18
- Chapter 1 21
- Mentor VIP Altera Edition 21
- What Is a Transaction? 22
- AXI4-Lite Transactions 22
- Chapter 2 27
- SystemVerilog API Overview 27
- Chapter 3 39
- SystemVerilog Master BFM 39
- SystemVerilog Master API 43
- Returns 44
- Example 58
- Chapter 4 63
- SystemVerilog Slave BFM 63
- SystemVerilog Slave API 68
- Arguments config_name 69
- Chapter 5 91
- SystemVerilog Monitor API 96
- Prototype 100
- Arguments 100
- April 2014 102
- SystemVerilog Monitor BFM 105
- Helper Functions 111
- SystemVerilog Tutorials 115
- Chapter 6 115
- BFM Master Test Program 116
- Verifying a Slave DUT 117
- Verifying a Master DUT 123
- Basic Slave API Definition 124
- *_valid_delay = 4 127
- *_ready_delay = 2 127
- Advanced Slave API Definition 129
- Initial Block 131
- Chapter 7 137
- VHDL API Overview 137
- Test Program VHDL 138
- Configuration 139
- Creating Transactions 139
- Transaction Definition 140
- Executing Transactions 144
- Waiting Events 145
- Access Transaction Record 146
- Operation Mode 147
- Channel Handshake Delay 147
- Handshake Delay 148
- Transaction Done 149
- Chapter 8 151
- VHDL Master BFM 151
- Master BFM Protocol Support 152
- Master Timing and Events 152
- Master BFM Configuration 152
- Master Assertions 155
- VHDL Master API 156
- Chapter 9 213
- VHDL Slave BFM 213
- Slave BFM Configuration 214
- Slave Assertions 216
- VHDL Slave API 217
- Operational 223
- Transaction 223
- Chapter 10 279
- VHDL Monitor BFM 279
- Monitor BFM Configuration 280
- Monitor Assertions 282
- VHDL Monitor API 283
- Chapter 11 335
- VHDL Tutorials 335
- BFM Slave Test Program 341
- Chapter 12 353
- Running the Qsys Tool 356
- Running a Simulation 359
- ModelSim Simulation 360
- Editing the modelsim.ini File 363
- Questa Simulation 364
- Cadence IES Simulation 364
- Synopsys VCS Simulation 366
- Appendix A 369
- AXI4-Lite Assertions 384
- Appendix B 385
- SystemVerilog Test Programs 385
- Appendix C 397
- VHDL Test Programs 397
- End-User License Agreement 409
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