Altera MAX 10 Embedded Memory Bedienungsanleitung PDF herunterladen (Seite 64)

Signal Required Description

wrreq Yes Assert this signal to request for a write operation.

Ensure that the following conditions are met:

• Do not assert the wrreq signal when the full (for the FIFO IP

core in SCFIFO mode) or wrfull (for the FIFO IP core in

DCFIFO mode) port is high. Enable the overflow protection

circuitry or turn on the Disable overflow checking. Writing to a

full FIFO will corrupt contents parameter so that the FIFO IP

core can automatically disable the wrreq signal when it is full.

• The wrreq signal must meet the functional timing requirement

based on the full or wrfull signal.

• Do not assert the wrreq signal during the deassertion of the aclr

signal. Violating this requirement creates a race condition

between the falling edge of the aclr signal and the rising edge of

the write clock if the wrreq port is set to high.

rdreq

Yes Assert this signal to request for a read operation. The rdreq signal

acts differently in normal synchronous FIFO mode and show-ahead

mode synchronous FIFO modes.

Ensure that the following conditions are met:

• Do not assert the rdreq signal when the empty (for the FIFO IP

core in SCFIFO mode) or rdempty (for the FIFO IP core in

DCFIFO mode) port is high. Enable the underflow protection

circuitry or turn on the Disable underflow checking. Reading

from an empty FIFO will corrupt contents parameter so that the

FIFO IP core can automatically disable the rdreq signal when it is

empty.

The rdreq signal must meet the functional timing requirement

based on the empty or rdempty signal.

sclr

No Assert this signal to clear all the output status ports, but the effect on

the q output may vary for different FIFO configurations. There are

no minimum number of clock cycles for aclr signals that must

remain active.

aclr No

Table 9-2: FIFO IP Core Output Signals

Signal Required Description

q Shows the data read from the read request operation. In SCFIFO and

DCFIFO modes, the width of the q port must be equal to the width of

the data port. If you manually instantiate the IPs, ensure that the

port width is equal to the How wide should the FIFO be? parameter.

In DCFIFO_MIXED_WIDTHS mode, the width of the q port can be

different from the width of the data port. If you manually instantiate

the IP, ensure that the width of the q port is equal to the Use a

different output width parameter. The IP supports a wide write port

with a narrow read port, and vice versa. However, the width ratio is

restricted by the type of RAM block, and in general, are in the power

of 2.

UG-M10MEMORY

2015.05.04

FIFO IP Core Signals for MAX 10 Devices

9-3

FIFO IP Core References

Altera Corporation

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