Altera MAX 10 Embedded Memory Bedienungsanleitung Seite 1

MAX 10 Embedded Memory User GuideSubscribeSend FeedbackUG-M10MEMORY2015.05.04101 Innovation DriveSan Jose, CA 95134www.altera.com

Address Clock Enable During Write Cycle WaveformFigure 2-5: Address Clock Enable Waveform During Write Cycle inclockwrenwraddressa0 a1 a2 a3 a4 a5a

Related Information• Internal Memory (RAM and ROM) User Guide.Resetting Registers in M9K BlocksThere are three ways to reset registers in the M9K bloc

Memory Operation Mode Related IP Core DescriptionSingle-port ROM ROM: 1-PORT IP Core Only one address port is available for readoperation.You can use

Related InformationMAX 10 Embedded Memory Related IPsMAX 10 Embedded Memory Clock ModesClock Mode DescriptionModesTrueDual-PortSimpleDual-PortSingle-P

Output Read Data in Simultaneous Read and WriteIf you perform a simultaneous read/write to the same address location using the read or write clock mod

• If your port width configuration (either the depth or the width) is more than the amount an internalmemory block can support, additional memory bloc

Read PortWrite Port8192 × 1 4096 × 2 2048 × 4 1024 × 8 512 × 16 1024 × 9 512 × 18512 × 16 Yes Yes Yes Yes Yes — —1024 × 9 — — — — — Yes Yes512 × 18 —

MAX 10 Embedded Memory DesignConsideration32015.05.04UG-M10MEMORYSubscribeSend FeedbackThere are several considerations that require your attention to

Same-Port Read-During-Write ModeThe same-port read-during-write mode applies to a single-port RAM or the same port of a true dual-portRAM.Table 3-1: O

Figure 3-3: Same Port Read-During-Write: Old Data Modeclk_awren_aaddress_adata_arden_aq_a (asynch)a0 a1A B C D E Fa0(old data) a1(old data)A B D EMixe

ContentsMAX 10 Embedded Memory Overview... 1-1MAX 10 Embedded Memory Architecture and Featu

Figure 3-4: Mixed-Port Read-During-Write: Old Data Modea ba (old data)b (old data)clk_a&bwren_aaddress_aq_b (asynch)rden_ba baddress_bdata_aA B C

Consider Power-Up State and Memory InitializationConsider the power-up state of the different types of memory blocks if you are designing logic thatev

Selecting Read-During-Write Output Choices• Single-port RAM only supports same-port read-during-write, and the clock mode must be eithersingle clock m

RAM: 1-Port IP Core References42015.05.04UG-M10MEMORYSubscribeSend FeedbackThe RAM: 1-Port IP core implements the single-port RAM memory mode.Figure 4

RAM: 1-Port IP Core Signals For MAX 10 DevicesTable 4-1: RAM:1-Port IP Core Input SignalsSignal Required Descriptiondata Yes Data input to the memory.

Signal Required Descriptioninclock Optional The following list describes which of your memoryclock must be connected to the inclock port, and portsync

Parameter Values DescriptionHow wide should the 'q' output bus be? 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15,16, 17, 18, 19, 20, 21,2

Parameter Values DescriptionCreate one clock enable signal for eachclock signal.On/Off Specifies whether to turn on the optionto create one clock enab

Parameter Values DescriptionNo, leave it blank On/Off Specifies the initial content of thememory. Initialize the memory tozero.Initialize memory conte

RAM: 2-PORT IP Core References52015.05.04UG-M10MEMORYSubscribeSend FeedbackThe RAM: 2-PORT IP core implements the simple dual-port RAM and true dual-p

RAM: 2-Port IP Core Parameters for MAX 10 Devices...5-9ROM: 1-PORT IP Core Refer

Figure 5-2: RAM: 2-Port IP Core Signals with the One Read Port and One Write Port, and Dual Clock: UseSeparate 'Read' and 'Write'

Figure 5-4: RAM: 2-Port IP Core Signals with the Two Read/Write Ports and Single Clock OptionsEnableddata_a[]wren_adata_b[]address_b[]addressstall_acl

Figure 5-5: RAM: 2-Port IP Core Signals with the Two Read/Write Ports and Dual Clock: Use Separate'Input' and 'Output' Clocks Opti

Figure 5-6: RAM: 2-Port IP Core Signals with the Two Read/Write Ports and Dual Clock: Use Separate forA and B Ports Options Enableddata_a[]wren_adata_

Signal Required Descriptionclock Yes The following list describes which of your memory clock mustbe connected to the clock port, and port synchronizat

Signal Required Descriptionbyteena_a Optional Byte enable input to mask the data_a port so that only specificbytes, nibbles, or bits of the data are w

Signal Required Descriptionwren_b Yes Write enable input for address_b port. The wren_b port isrequired if you set the operation_mode parameter to BID

Signal Required Descriptionrden_a Optional Read enable input for address_a port. The rden_a port issupported depending on your selected memory mode an

Option Legal Values DescriptionHow will you be using the dual port RAM?• With one read port andone write port• With two read/write portsSpecifies how

Option Legal Values DescriptionWhat should the memory block type be?• Auto• M9K• LCsSpecifies the memory blocktype. The types of memoryblock that are

MAX 10 Embedded Memory Overview12015.05.04UG-M10MEMORYSubscribeSend FeedbackMAX® 10 embedded memory block is optimized for applications such as high t

Option Legal Values DescriptionWhat clocking method would you like touse?When you select With oneread port and one write port,the following values are

Option Legal Values DescriptionByte Enable Ports Create byte enable forport AOn/Off Specifies whether to create abyte enable for Port A and B.Turn on

Option Legal Values DescriptionCreate one clock enable signal for eachclock signal.On/Off Specifies whether to turn onthe option to create oneclock en

Option Legal Values DescriptionMore Option When you select Withone read port and onewrite port, thefollowing options areavailable:• ‘rdaddress’ port•

Option Legal Values DescriptionDo not analyze the timing between writeand read operation. Metastability issues areprevented by never writing and readi

Option Legal Values DescriptionDo you want to specify the initial contentof the memory?• No, leave it blank• Yes, use this file for thememory content

ROM: 1-PORT IP Core References62015.05.04UG-M10MEMORYSubscribeSend FeedbackThe ROM: 1-PORT IP core implements the single-port ROM memory mode.Figure 6

Figure 6-2: ROM: 1-PORT IP Core Signals with the Dual Clock: Use Separate 'Input' and 'Output' ClocksOption Enabledaddressstall_ao

Signal Required Descriptionclock Yes The following list describes which of your memoryclock must be connected to the clock port, and portsynchronizati

Signal Required Descriptionoutclocken Optional Clock enable input for outclock port.Table 6-2: ROM: 1-PORT IP Core Output SignalsSignal Required Descr

MAX 10 Embedded Memory Architecture andFeatures22015.05.04UG-M10MEMORYSubscribeSend FeedbackThe MAX 10 embedded memory structure consists of 9,216-bit

Option Legal Values DescriptionWhat clocking method would you like touse?• Single clock• Dual clock: use separate‘input’ and ‘output’ clocksSpecifies

Option Legal Values DescriptionMore Options• 'address' port• 'q' portOn/Off Specifies whether theaddress and q ports arecleared by

ROM: 2-PORT IP Core References72015.05.04UG-M10MEMORYSubscribeSend FeedbackThis IP core implements the dual-port ROM memory mode. The dual-port ROM ha

Figure 7-2: ROM: 2-PORT IP Core Signals with the Dual Clock: Use Separate 'Input' and 'Output' ClocksOption Enabledaddress_b[]addr

ROM: 2-PORT IP Core Signals for MAX 10 DevicesTable 7-1: ROM: 2-PORT IP Core Input SignalsSignal Required Descriptionaddress_a Yes Address input to po

Signal Required Descriptioninclock Yes The following list describes which of your memory clock must beconnected to the inclock port, and port synchron

Signal Required Descriptionq_b Yes Data output from port B of the memory. The q_b port is requiredif you set the operation_mode parameter to the follo

Option Legal Values DescriptionWhat clocking method would you like touse?• Single clock• Dual clock: useseparate ‘input’ and‘output’ clocks• Dual cloc

Option Legal Values DescriptionMore Options• Clock enable options• Use clock enablefor port A inputregisters• Use clock enablefor port A outputregiste

Option Legal Values DescriptionDo you want to specify the initial contentof the memory?Yes, use this file for thememory content dataSpecifies the init

The rden and wren control signals control the read and write operations for each port of the M9Kmemory blocks. You can disable the rden or wren signal

Shift Register (RAM-based) IP Core References82015.05.04UG-M10MEMORYSubscribeSend FeedbackThe Shift Register (RAM-based) IP core contains additional f

Signal Required Descriptiontaps[] Yes Output from the regularly spaced taps along the shift register. Outputport WIDTH * NUMBER_OF_TAPS wide. This por

FIFO IP Core References92015.05.04UG-M10MEMORYSubscribeSend FeedbackThe FIFO IP core implements the FIFO mode, enabling you to use the memory blocks a

Figure 9-2: FIFO IP Core: DCFIFO Mode Signalsdata[]wrreqwrclkwrfullwremptywrusedw[]rdreqrdclkq[]rdfullrdemptyrdusedw[]aclrFIFO IP Core Signals for MAX

Signal Required Descriptionwrreq Yes Assert this signal to request for a write operation.Ensure that the following conditions are met:• Do not assert

Signal Required DescriptionfullNoWhen asserted, the FIFO IP core is considered full. Do not performwrite request operation when the FIFO IP core is fu

Parameter HDL Parameter DescriptionUsedw[] lpm_widthu Specifies the width of the usedw port for the FIFO IP corein SCFIFO mode, or the width of the rd

Parameter HDL Parameter DescriptionHow many sync stages?(2)rdsync_delaypipeSpecifies the number of synchronization stages in the crossclock domain. Th

Parameter HDL Parameter DescriptionWhich type of optimiza‐tion do you want?(2)clocks_are_synchronizedSpecifies whether or not the write and read clock

ALTMEMMULT IP Core References102015.05.04UG-M10MEMORYSubscribeSend FeedbackThe ALTMEMMULT IP core creates only memory-based multipliers using on-chip

If you... ...Then• Activate the read enable during a writeoperation, or• Do not create a read-enable signalThe output port shows:• the new data being

Signal Required Descriptionsload_data No Synchronous load data input port. Signal that specifies new multiplicationoperation and cancels any existing

Additional Information for MAX 10 EmbeddedMemory User GuideA2015.05.04UG-M10MEMORYSubscribeSend FeedbackDocument Revision History for MAX 10 Embedded

Data Byte OutputIf you... ...ThenDeassert a byte-enable bit during a write cycle The old data in the memory appears in thecorresponding data-byte outp

Address Clock Enable Support• The address clock enable feature holds the previous address value for as long as the address clockenable signal (address