Altera MAX 10 Embedded Memory Bedienungsanleitung PDF herunterladen (Seite 54)

ROM: 2-PORT IP Core Signals for MAX 10 Devices

Table 7-1: ROM: 2-PORT IP Core Input Signals

Signal Required Description

address_a Yes Address input to port A of the memory. The address_a port is

required for all operation modes.

rden_a Optional Read enable input for address_a port. The rden_a port is

supported depending on your selected memory mode and memory

block.

address_b Optional Address input to port B of the memory. The address_b port is

required if the operation_mode parameter is set to the following

values:

• DUAL_PORT

• BIDIR_DUAL_PORT

rden_b Optional Read enable input for address_b port. The rden_b port is

supported depending on your selected memory mode and memory

block.

clock Yes The following list describes which of your memory clock must be

connected to the clock port, and port synchronization in different

clock modes:

• Single clock—Connect your single source clock to clock port.

All registered ports are synchronized by the same source clock.

• Read/Write—Connect your write clock to clock port. All

registered ports related to write operation, such as data_a port,

address_a port, wren_a port, and byteena_a port are

synchronized by the write clock.

• Input/Output—Connect your input clock to clock port. All

registered input ports are synchronized by the input clock.

• Independent clock—Connect your port A clock to clock port.

All registered input and output ports of port A are synchron‐

ized by the port A clock.

addressstall_a

Optional Address clock enable input to hold the previous address of

address_a port for as long as the addressstall_a port is high.

addressstall_b Optional Address clock enable input to hold the previous address of

address_b port for as long as the addressstall_b port is high.

UG-M10MEMORY

2015.05.04

ROM: 2-PORT IP Core Signals for MAX 10 Devices

7-3

ROM: 2-PORT IP Core References

Altera Corporation

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Altera MAX 10 Embedded Memory Bedienungsanleitung Seite 54