
Read Port
Write Port
8192 × 1 4096 × 2 2048 × 4 1024 × 8 512 × 16 1024 × 9 512 × 18
512 × 16 Yes Yes Yes Yes Yes — —
1024 × 9 — — — — — Yes Yes
512 × 18 — — — — — Yes Yes
Maximum Block Depth Configuration
The Set the maximum block depth parameter allows you to set the maximum block depth of the
dedicated memory block you use. You can slice the memory block to your desired maximum block depth.
For example, the capacity of an M9K block is 9,216 bits, and the default memory depth is 8K, in which
each address is capable of storing 1 bit (8K × 1). If you set the maximum block depth to 512, the M9K
block is sliced to a depth of 512 and each address is capable of storing up to 18 bits (512 × 18).
Use this parameter to save power usage in your devices and to reduce the total number of memory blocks
used. However, this parameter might increase the number of LEs and affects the design performance.
When the RAM is sliced shallower, the dynamic power usage decreases. However, for a RAM block with a
depth of 256, the power used by the extra LEs starts to outweigh the power gain achieved by shallower
slices.
The maximum block depth must be in a power of two, and the valid values vary among different
dedicated memory blocks.
This table lists the valid range of maximum block depth for M9K memory blocks.
Table 2-5: Valid Range of Maximum Block Depth for M9K Memory Blocks
Memory Block Valid Range
M9K 256 - 8K. The maximum block depth must be in a power of two.
The IP parameter editor prompts an error message if you enter an invalid value for the maximum block
depth. Altera recommends that you set the value of the Set the maximum block depth parameter to Auto
if you are unsure of the appropriate maximum block depth to set or the setting is not important for your
design. The Auto setting enables the Compiler to select the maximum block depth with the appropriate
port width configuration for the type of internal memory block of your memory.
2-12
Maximum Block Depth Configuration
UG-M10MEMORY
2015.05.04
Altera Corporation
MAX 10 Embedded Memory Architecture and Features
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