Altera Arria 10 Avalon-ST Bedienungsanleitung

Arria 10 Avalon-ST Interface for PCIeSolutionsUser GuideLast updated for Altera Complete Design Suite: 15.0SubscribeSend FeedbackUG-01145_avst2015.05.

Table 1-2: Feature Comparison for all Hard IP for PCI Express IP CoresThe table compares the features of the four Hard IP for PCI Express IP Cores.Fea

Signal Direction Descriptionpld_clk_inuseOutput When asserted, indicates that the Hard IP Transaction Layer isusing the pld_clk as its clock and is re

Signal Direction Descriptioncurrentspeed[1:0]Output Indicates the current speed of the PCIe link. The followingencodings are defined:• 2b’00: Undefine

ECRC ForwardingOn the Avalon-ST interface, the ECRC field follows the same alignment rules as payload data. For packetswith payload, the ECRC is appen

Interrupts for EndpointsRefer to Interrupts for detailed information about all interrupt mechanisms.Table 6-9: Interrupt Signals for EndpointsSignal D

Interrupts for Root PortsTable 6-10: Interrupt Signals for Root PortsSignal Direction Descriptionint_status[3:0]Output These signals drive legacy inte

Table 6-11: Completion Signals for the Avalon-ST InterfaceSignal DirectionDescriptioncpl_err[6:0]Input Completion error. This signal reports completio

Signal DirectionDescription• cpl_err[4]: Unsupported Request (UR) error for posted TLP.The Application Layer asserts this signal to treat a posted req

Parity SignalsYou enable parity checking by selecting Enable byte parity ports on the Avalon-ST interface under theSystem Settings heading of the para

Signal Name Direction Descriptioncfg_par_errOutput When asserted for a single cycle, indicates that a parity error wasdetected in a TLP that was route

When a LMI write has a timing conflict with configuration TLP access, the configuration TLP accesseshave higher priority. LMI writes are held and exec

Feature Avalon-ST Interface Avalon-MMInterfaceAvalon-MM DMA Avalon-ST Interface with SR-IOVAutomaticallyhandle out-of-ordercompletions(transparent tot

Figure 6-36: LMI WriteOnly writeable configuration bits are overwritten by this operation. Read-only bits are not affected. LMIwrite operations are no

Signal Direction DescriptionInput • [0]: Attention button pressed. This signal should be assertedwhen the attention button is pressed. If no attention

tl_cfg_sts Configuration Space Register Description[46:31] Link Status Register[15:0] Records the following link status informa‐tion:• Bit 15: link au

Configuration Space Register Access TimingFigure 6-37: tl_cfg_ctl TimingThe following figure shows typical traffic on the tl_cfg_ctl bus. The tl_cfg_a

Figure 6-38: Multiplexed Configuration Register Information Available on tl_cfg_ctlFields in blue are available only for Root Ports.01cfg_dev_ctrl[15:

Register Width Direction Descriptioncfg_link_ctrl16 Output cfg_link_ctrl[15:0]is the primary Link Controlof the PCI Express capability structure.For G

Register Width Direction Descriptioncfg_msi_addr64 Output cfg_msi_add[63:32] is the message signaledinterrupt (MSI) upper message address. cfg_msi_add

Register Width Direction Descriptioncfg_tcvcmap24 Output Configuration traffic class (TC)/virtual channel(VC) mapping. The Application Layer uses this

Bit(s) Field Description[6:4] multiple messageenableThis field indicates permitted values for MSI signals. For example,if “100” is written to this fie

Signal Direction Descriptionhip_reconfig_address[9:0]Input The 10-bit reconfiguration address.hip_reconfig_readInput Read signal. This interface is no

Transaction LayerPacket type (TLP)(transmit support)Avalon-ST Interface Avalon-MMInterfaceAvalon-MM DMA Avalon-ST Interface with SR-IOVMemory ReadLock

Figure 6-40: Hard IP Reconfiguration Bus Timing of Read-Only Registersavmm_clkhip_reconfig_rst_nuser_modeser_shift_loadinterface_selavmm_wravmm_wrdata

Signal Direction Descriptionpm_eventInput Power Management Event. This signal is only available forEndpoints.The Endpoint initiates a a power_manageme

Table 6-20: Power Management Capabilities Register Field DescriptionsBits Field Description[31:24]Data registerThis field indicates in which power sta

Physical Layer Interface SignalsAltera provides an integrated solution with the Transaction, Data Link and Physical Layers. The IPParameter Editor gen

Table 6-22: PIPE Interface SignalsSignal Direction Descriptiontxdata0[31:0]Output Transmit data <n>. This bus transmits data on lane <n>.t

Signal Direction Descriptionpowerdown0[1:0] Output Power down <n>. This signal requests the PHY to change itspower state to the specified state

Signal Direction Descriptionsim_pipe_rate[1:0]Output The 2-bit encodings have the following meanings:• 2’b00: Gen1 rate (2.5 Gbps)• 2’b01: Gen2 rate (

Signal Direction Description• 5’b11010: Speed.Recovery• 5’b11011: Recovery.Equalization, Phase 0• 5’b11100: Recovery.Equalization, Phase 1• 5’b11101:

Test SignalsTable 6-23: Test Interface SignalsThe test_in bus provides run-time control and monitoring of the internal state of the IP core.Signal Dir

Registers72015.05.04UG-01145_avstSubscribeSend FeedbackCorrespondence between Configuration Space Registers and the PCIeSpecificationTable 7-1: Corres

Transaction LayerPacket type (TLP)(transmit support)Avalon-ST Interface Avalon-MMInterfaceAvalon-MM DMA Avalon-ST Interface with SR-IOVFetch and AddAt

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x170:0x17C Reserved N/A0x180:0x1FC Virtual channel arbit

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x018 Base Address 2Secondary Latency Timer, Subordinate

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x058 Message Upper Address MSI and MSI-X Capability Stru

Type 0 Configuration Space RegistersFigure 7-1: Type 0 Configuration Space Registers - Byte Address Offsets and LayoutEndpoints store configuration da

Figure 7-3: MSI-X Capability Structure0x0680x06C0x070Message Control Next Cap PtrMSI-X Table OffsetMSI-X Pending Bit Array (PBA) Offset31 24 23 16 15

Figure 7-6: PCI Express Capability Structure - Byte Address Offsets and LayoutIn the following table showing the PCI Express Capability Structure, reg

Altera-Defined VSEC RegistersFigure 7-7: VSEC RegistersThis extended capability structure supports Configuration via Protocol (CvP) programming and de

Table 7-3: Altera‑Defined Vendor Specific HeaderYou can specify these values when you instantiate the Hard IP. These registers are read-only at run-ti

Table 7-7: CvP StatusThe CvP Status register allows software to monitor the CvP status signals.Bits Register Description Reset Value Access[31:26] Res

Bits Register Description Reset Value Access[1] HIP_CLK_SEL. Selects between PMA and fabric clock when USER_MODE = 1 and PLD_CORE_READY = 1. The follo

Device Family SupportTable 1-5: Device Family SupportDevice Family SupportArria 10Preliminary. The IP core is verified with prelimi‐nary timing models

Bits Register Description Reset Value Access[1] START_XFER. Sets the CvP output to the FPGA control blockindicating the start of a transfer.1’b0 RW[0]

Bits Register Description Reset Value Access[0] Mask for the RX buffer uncorrectable ECC error. 1b’1 RWSUncorrectable Internal Error Status RegisterTa

Bits Register DescriptionResetValueAccess[1] When set, indicates a retry buffer uncorrectable ECC error.0RW1CS[0] When set, indicates a RX buffer unco

Bits Register Description Reset Value Access[5] When set, indicates a configuration error has been detected inCvP mode which is reported as correctabl

Arria 10 Reset and Clocks82015.05.04UG-01145_avstSubscribeSend FeedbackFigure 8-1: Reset Controller in Arria 10 DevicesExample Design<instance_name

Reset Sequence for Hard IP for PCI Express IP Core and Application LayerFigure 8-2: Hard IP for PCI Express and Application Logic Reset SequenceYour A

Figure 8-3: RX Transceiver Reset Sequencebusy_xcvr_reconfigrx_pll_lockedrx_analogresetltssmstate[4:0]txdetectrx_loopbackpipe_phystatuspipe_rxstatus[2:

For descriptions of the available reset signals, refer to Reset Signals, Status, and Link Training Signals.Related InformationReset, Status, and Link

As this figure indicates, the IP core includes the following clock domains:coreclkout_hipTable 8-1: Application Layer Clock Frequency for All Combinat

Link Width Maximum Link Rate Avalon Interface Width coreclkout_hip×4 Gen3 256 125 MHz×8 Gen3 256 250 MHzpld_clkcoreclkout_hip can drive the Applicatio

Figure 1-2: PCI Express Application with a Single Root Port and EndpointThe following figure shows a PCI Express link between two Arria 10 FPGAs.Alter

Interrupts92015.05.04UG-01145_avstSubscribeSend FeedbackInterrupts for EndpointsThe Arria 10 Hard IP for PCI Express provides support for PCI Express

Figure 9-1: MSI Handler BlockMSI HandlerBlockapp_msi_reqapp_msi_ackapp_msi_tc[2:0]app_msi_num[4:0]pex_msi_numapp_int_stscfg_msicsr[15:0]The following

Figure 9-3: MSI Request ExampleEndpoint8 Requested2 AllocatedRoot ComplexCPUInterrupt RegisterRootPortInterruptBlockThe following table describes thre

Figure 9-4: MSI Interrupt Signals Timingclkapp_msi_reqapp_msi_tc[2:0]app_msi_num[4:0]app_msi_ack1 2 3 5 647validvalidRelated InformationCorrespondence

Figure 9-5: MSI-X Interrupt ComponentsHostRXTXRXTXPCIe with Avalon-ST I/FMSI-X TableIRQProcessorMSI-X PBAIRQ SourceApplication LayerHost SW Programs

Figure 9-7: MSI-X PBA TablePending Bits 0 through 63Pending Bits 64 through 127Pending Bits ((N - 1) div 64) × 64 through N - 1QWORD 0QWORD 1QWORD ((

Interrupts for Root PortsIn Root Port mode, the Arria 10 Hard IP for PCI Express receives interrupts through two differentmechanisms:• MSI—Root Ports

Error Handling102015.05.04UG-01145_avstSubscribeSend FeedbackEach PCI Express compliant device must implement a basic level of error management and ca

Physical Layer ErrorsTable 10-2: Errors Detected by the Physical LayerThe following table describes errors detected by the Physical Layer. Physical La

Transaction Layer ErrorsTable 10-4: Errors Detected by the Transaction LayerError Type DescriptionPoisoned TLP received Uncorrectable(non-fatal)This e

PCIe LinkPCIe Hard IPRPSwitchPCIeHard IPRPUser ApplicationLogicPCIe Hard IPEPPCIe LinkPCIe LinkUser ApplicationLogicAltera FPGA Hard IP for PCI Expres

Error Type DescriptionIn all cases the TLP is deleted in the Hard IP block andnot presented to the Application Layer. If the TLP is anon-posted reques

Error Type DescriptionUnexpected completion Uncorrectable(non-fatal)This error is caused by an unexpected completiontransaction. The Hard IP block han

Error Type DescriptionMalformed TLP Uncorrectable(fatal)This error is caused by any of the following conditions:• The data payload of a received TLP e

Poisoned TLPs can also set the parity error bits in the PCI Configuration Space Status register.Table 10-5: Parity Error ConditionsStatus Bit Conditio

Figure 10-2: Correctable Error Status RegisterThe default value of all the bits of this register is 0. An error status bit that is set indicates that

IP Core Architecture112014.08.18UG-01145_avstSubscribeSend FeedbackThe Arria 10 Hard IP for PCI Express implements the complete PCI Express protocol s

Figure 11-1: Arria 10 Hard IP for PCI Express Using the Avalon-ST InterfaceClockDomainCrossing(CDC)Data LinkLayer(DLL)Transaction Layer (TL)PHYMAC Har

The following interfaces provide access to the Application Layer’s Configuration Space Registers:• The LMI interface• The Avalon-MM PCIe reconfigurati

Clocks and ResetThe PCI Express Base Specification requires an input reference clock, which is called refclk in this design.The PCI Express Base Speci

• The Gen1, Gen2, and Gen3 simulation models support PIPE and serial simulation.• For Gen3, the Altera BFM bypasses Gen3 Phase 2 and Phase 3 Equalizat

Figure 1-4: Example Design Preset ParametersYou can download the Qsys example designs for the Arria 10 Hard IP for PCI Express from the<install_dir

Figure 11-2: Architecture of the Transaction Layer: Dedicated Receive BufferTransaction Layer TX DatapathTransaction Layer RX DatapathAvalon-STRX Cont

The Configuration Space also generates all messages (PME#, INT, error, slot power limit), MSI requests,and completion packets from configuration reque

Figure 11-3: Error Handing in Configuration Space Bypass ModeTransaction Layer of the Hard IP for PCI ExpressApplication Layer(Soft Logic)Avalon-ST TX

• The Transaction Layer sends poisoned TLPs on the Avalon-ST RX interface for completions and errorhandling by the Application Layer. These errors are

Protocol Extensions SupportedThe Transaction Layer supports the following protocol extensions:• TLP Processing Hints (TPH)—Supports both a Requester a

Figure 11-4: Data Link LayerTo Transaction LayerTx Transaction LayerPacket Description & DataTransaction LayerPacket GeneratorRetry BufferTo Physi

• ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and generates the sequencenumber of transmitted packets.• Transaction Layer Packet Checker—T

Figure 11-5: Physical Layer ArchitectureScrambler8B10BEncoderLane nTX+ / TX-Scrambler8B10BEncoderLane 0TX+ / TX-Descrambler8B10BDecoderLane nRX+ / RX-

The PHYMAC block comprises four main sub-blocks:• MAC Lane—Both the RX and the TX path use this block.• On the RX side, the block decodes the Physical

Transaction Layer Protocol (TLP) Details122015.05.04UG-01145_avstSubscribeSend FeedbackSupported Message TypesINTX MessagesThe following table describ

IP Core VerificationTo ensure compliance with the PCI Express specification, Altera performs extensive verification. Thesimulation environment uses mu

MessageRootPortEndpointGenerated byCommentsAppLayerCore Core(withAppLayerinput)Deassert_INTBReceive Transmit No No NoDeassert_INTCReceive Transmit No

Error Signaling MessagesTable 12-3: Error Signaling MessagesMessageRootPortEndpointGenerated byCommentsAppLayerCore Core (withApp Layerinput)ERR_CORRX

Locked Transaction MessageTable 12-4: Locked Transaction MessageMessage Root Port EndpointGenerated byCommentsAppLayerCore Core (withApp Layerinput)Un

Message Root Port EndpointGenerated byCommentsAppLayerCore Core (withApp Layerinput)VendorDefinedType 1TransmitReceiveTransmitReceiveYes No NoHot Plug

Message Root Port EndpointGenerated byCommentsAppLayerCore Core (withApp Layerinput)AttentionButton_Pressed(Endpoint only)Receive Transmit No No YesN/

• The Type 0 Configuration TLPs are only routed to the Configuration Space of the Hard IP and are notsent downstream on the PCI Express link.• The Typ

• A Memory Write or Message Request with the Relaxed Ordering Attribute bit clear (b’0) must not passany other Memory Write or Message Request.• A Mem

Can the Row Passthe Column?Posted Req Non Posted ReqCompletionMemory Write orMessage ReqRead Request I/O or Cfg Write ReqCmplCmpl NoY/NNoNoYes Yes Yes

Figure 12-1: Design Including Legacy PCI Buses Requiring Strong OrderingProducerPCI-toPCI BridgePCI BusFlagPostedWrite BufferConsumerPCI BusMemoryRead

Figure 12-2: PCI Express Design Using Relaxed OrderingRootComplexPCIeEndpointSwitchWrite BufferFullCPUMemoryPCIe Bridge to PCI or PCI-XLegacyEndpointP

• Is your design an Endpoint or Root Port?• What Generation do you intend to implement?• What link width do you intend to implement?• What bandwidth d

Throughput Optimization132015.05.04UG-01145_avstSubscribeSend FeedbackThe PCI Express Base Specification defines a flow control mechanism to ensure ef

Figure 13-1: Flow Control Update LoopCreditsConsumedCounterCreditLimitData PacketFlowControlGatingLogic(CreditCheck)AllowIncrRxBufferData PacketCredit

counter. Essentially, this means the data sink knows the data source has less than a fullMAX_PAYLOAD worth of credits, and therefore is starving.b. Wh

Nevertheless, maintaining maximum throughput of completion data packets is important. Endpointsmust offer an infinite number of completion credits. En

Design Implementation142015.05.04UG-01145_avstSubscribeSend FeedbackCompleting your design includes additional steps to specify analog properties, pin

entering user mode. Link training occurs after calibration. Refer to Reset Sequence for Hard IP for PCIExpress IP Core and Application Layer for a des

Optional Features152015.05.04UG-01145_avstSubscribeSend FeedbackConfiguration via Protocol (CvP)The Hard IP for PCI Express architecture has an option

CvP has the following advantages:• Provides a simpler software model for configuration. A smart host can use the PCIe protocol and theapplication topo

Table 15-1: ECRC Operation on RX PathECRC Forwarding ECRC Check Enable(5)ECRC Status Error TLP Forward to Application LayerNoNonone No Forwardedgood N

Table 15-2: ECRC Generation and Forwarding on TX PathAll unspecified cases are unsupported and the behavior of the Hard IP is unknown.ECRC Forwarding

ContentsDatasheet... 1-1Arria 10 Avalon-ST I

Getting Started with the Arria 10 Hard IP for PCIExpress22015.05.04UG-01145_avstSubscribeSend FeedbackThis section provides instructions to help you q

Hard IP Reconfiguration162015.05.04UG-01145_avstSubscribeSend FeedbackThe Arria 10 Hard IP for PCI Express reconfiguration block allows you to dynamic

Testbench and Design Example172015.05.04UG-01145_avstSubscribeSend FeedbackThis chapter introduces the Root Port or Endpoint design example including

Your Application Layer design may need to handle at least the following scenarios that are not possible tocreate with the Altera testbench and the Roo

The top-level of the testbench instantiates four main modules:• <qsys_systemname>— This is the example Endpoint design. For more information abo

The testbench has routines that perform the following tasks:• Generates the reference clock for the Endpoint at the required frequency.• Provides a re

Note: The chaining DMA design example only supports dword-aligned accesses. The chaining DMAdesign example does not support ECRC forwarding.The BFM dr

The block diagram contains the following elements:• Endpoint DMA write and read requester modules.• The chaining DMA design example connects to the Av

module monitors performance and acknowledges incoming message TLPs. Each DMA module consists ofthese components:• Control register module—The RC progr

• al tpcierd_dma_prg_reg—This module contains the chaining DMA control registers which getprogrammed by the software application or BFM driver.• altpc

Memory BAR Mapping32-bit BAR232-bit BAR364-bit BAR3:2Maps to DMA Read and DMA write control and status registers, aminimum of 256 bytes.32-bit BAR432-

For a detailed explanation of this example design, refer to the Testbench and Design Example chapter. Ifyou choose the parameters specified in this ch

Addr Register Name Bits[31:]24 Bit[23:16] Bit[15:0]0x1CDMA Rd Cntl DW3Reserved Reserved RCLAST–Idx of the lastdescriptor to processThe following table

Table 17-4: Chaining DMA Status Register DefinitionsAddr Register NameBits[31:24] Bits[23:16] Bits[15:0]0x20DMA Wr Status HiFor field definitions refe

Bit Field Description16Write DMA descriptorFIFO emptyIndicates that there are no more descriptors pending in the writeDMA.[15:0]Write DMA EPLASIndicat

tors. The Endpoint chaining DMA application accesses the Chaining DMA descriptor table for tworeasons:• To iteratively retrieve four-dword descriptors

Byte AddressOffset to BaseSourceDescriptor Type Description0x ..0Descriptor <n>Control fields, DMA length0x ..4 Endpoint address0x ..8 RC addres

Descriptor Field EndpointAccessRC Access DescriptionRC AddressUpper DWORDR R/W Specifies the upper base address of the memorytransfer on the RC site.R

a. DMA write—The driver programs the chaining DMA to write the data from its Endpoint memoryback to the BFM shared memory. The descriptor control fiel

Table 17-12: Write Descriptor 1Offset in BFMShared MemoryValue DescriptionDW0 0x820 1,024 Transfer length in dwords and control bits as described inBi

Table 17-14: DMA Control Register Setup for DMA WriteOffset in DMAControl Register(BAR2)Value DescriptionDW0 0x0 3 Number of descriptors and control b

Table 17-16: Read Descriptor 1Offset in BFMShared MemoryValue DescriptionDW0 0x920 1,024 Transfer length in dwords and control bits as described in on

The example design includes the following components:• DUT—This is Gen1 ×8 Endpoint. For your own design, you can select the data rate, number of lane

Offset in DMA ControlRegisters (BAR2)Value DescriptionDW1 0x14 0 BFM shared memoryupper address valueDW2 0x18 0x900 BFM shared memorylower address val

Figure 17-3: Root Port Design Example Root Port Variation(variation_name.v)Avalon-ST Interface(altpcietb_bfm_vc_intf)Test Driver(altpcietb_bfm_driver_

The top-level of the testbench instantiates the following key files:• altlpcietb_bfm_top_ep.v— this is the Endpoint BFM. This file also instantiates t

Figure 17-4: Root Port BFMBFM Shared Memory(altpcietb_bfm_shmem _common)BFM Log Interface(altpcietb_bfm_log_common)Root Port RTL Model (altpcietb_bfm_

• BFM Read/Write Request Functions(altpcietb_bfm_driver_rp.v)—These functions provide the basicBFM calls for PCI Express read and write requests. For

The ebfm_cfg_rp_ep executes the following steps to initialize the Configuration Space:1. Sets the Root Port Configuration Space to enable the Root Por

configuration is unlikely to be useful in real systems. If the procedure is unable to assign the BARs,it displays an error message and stops the simul

Offset (Bytes) Description+60 ReservedThe configuration routine does not configure any advanced PCI Express capabilities such as the AERcapability.Bes

Figure 17-6: Memory Space Layout—No Limit Root Complex Shared MemoryUnusedUnusedConfiguration ScratchSpace Used byRoutines - NotWriteable by UserCal

Figure 17-7: I/O Address Space Root Complex Shared MemoryUnusedConfiguration ScratchSpace Used by BFMRoutines - NotWriteable by UserCalls or EndpointB

The simulation includes the following stages:• Link training• Configuration• DMA reads and writes• Root Port to Endpoint memory reads and writesDisabl

Verilog HDL include file altpcietb_bfm_driver_rp.v. The complete list of available procedures andfunctions is as follows:• ebfm_barwr—writes data from

Location altpcietb_bfm_rdwr.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory. The bar_table structure stores the add

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory. The bar_table structure stores th

Argumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory. The bar_table structure stores the address assigned toeach BAR so t

ebfm_cfgwr_imm_wait ProcedureThe ebfm_cfgwr_imm_wait procedure writes up to four bytes of data to the specified configurationregister. This procedure

Location altpcietb_bfm_driver_rp.vSyntax ebfm_cfgwr_imm_nowt(bus_num, dev_num, fnc_num, imm_regb_adr, regb_len, imm_data)Argumentsbus_numPCI Express b

Location altpcietb_bfm_driver_rp.vArgumentsbus_numPCI Express bus number of the target device.dev_numPCI Express device number of the target device.fn

Location altpcietb_bfm_driver_rp.vArgumentsbus_numPCI Express bus number of the target device.dev_numPCI Express device number of the target device.fn

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory. This routine populates the bar_ta

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory.bar_numBAR number to analyze.log2_

Time TLP Type Payload(Bytes)TLP Header18021 RX CfgRd0 0004 04000001_0000010F_0108002C18053 RX CfgRd0 0004 04000001_0000030F_0108003C18085 RX MRd 0000

Constant DescriptionSHMEM_FILL_QWORD_INCSpecifies a data pattern of incrementing 64-bit qwords(0x0000000000000000, 0x0000000000000001,0x00000000000000

shmem_display Verilog HDL FunctionThe shmem_display Verilog HDL function displays a block of data from the BFM shared memory.Location altpcietb_bfm_dr

Related InformationShared Memory Constants on page 17-39shmem_chk_ok FunctionThe shmem_chk_ok function checks a block of BFM shared memory against a s

Table 17-21: Log MessagesConstant(MessageType)Description Mask BitNoDisplayby DefaultSimulationStops byDefaultMessagePrefixEBFM_MSG_DEBUGSpecifies deb

Constant(MessageType)Description Mask BitNoDisplayby DefaultSimulationStops byDefaultMessagePrefixEBFM_MSG_ERROR_FATAL_TB_ERRUsed for BFM test driver

ebfm_log_stop_sim Verilog HDL FunctionThe ebfm_log_stop_sim procedure stops the simulation.Location altpcietb_bfm_driver_rp.vSyntax Verilog VHDL: retu

Related InformationBFM Log and Message Procedures on page 17-42ebfm_log_open Verilog HDL FunctionThe ebfm_log_open procedure opens a log file of the s

Location altpcietb_bfm_driver_rp.vSyntax string:= himage(vec)ArgumentrangevecInput data type reg with a range of 7:0.ReturnrangestringReturns a 2-digi

Locationaltpcietb_bfm_driver_rp.vSyntax string:= himage(vec)ArgumentrangevecInput data type reg with a range of 63:0.ReturnrangestringReturns a 16-dig

dimage3This function creates a three-digit decimal string representation of the input argument that can beconcatenated into a larger message string an

a. The working directory shown is correct. You do not have to change it.b. For the project name, click the browse button browse to the synthesis direc

Locationaltpcietb_bfm_driver_rp.vReturnrangestringReturns a 5-digit decimal representation of the input argumentthat is padded with leading 0s if nece

chained_dma_test ProcedureThe chained_dma_test procedure is the top-level procedure that runs the chaining DMA read and thechaining DMA writeLocation

Location altpcietb_bfm_driver_rp.vSyntaxdma_wr_test (bar_table, bar_num, use_msi, use_eplast)Argumentsbar_tableAddress of the Endpoint bar_table struc

Location altpcietb_bfm_driver_rp.vSyntaxdma_set_header (bar_table, bar_num, Descriptor_size, direction, Use_msi,Use_eplast, Bdt_msb, Bdt_lab, Msi_numb

Location altpcietb_bfm_driver_rp.vArgumentsrc_addrAddress of the BFM shared memory that is being polled.rc_dataExpected data value of the that is bein

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory.bar_numBAR number to analyze.Bus_n

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemoryallowed_barsOne hot 6 bits BAR sele

Related InformationBFM Log and Message Procedures on page 17-42Setting Up SimulationChanging the simulation parameters reduces simulation time and pro

Complete the following steps to disable the scrambler:1. Open <work_dir>/<variant>/testbench/<variant>_tb/simulation/submodules/altp

Debugging182015.05.04UG-01145_avstSubscribeSend FeedbackAs you bring up your PCI Express system, you may face a number of issues related to FPGA confi

Files Generated for Altera IP CoresFigure 2-3: IP Core Generated Files<your_testbench>_tb.csv<your_testbench>_tb.spd<your_ip>.cmp -

The following sections, describe how to debug the hardware bring-up flow. Altera recommends asystematic approach to diagnosing bring-up issues as illu

Table 18-2: Link Hangs in L0Possible Causes Symptoms and Root Causes Workarounds and SolutionsAvalon-ST signalingviolates Avalon-STprotocolAvalon-ST p

Possible Causes Symptoms and Root Causes Workarounds and SolutionsMalformed TLP istransmittedRefer to the error log file to findthe last good packet t

Use Third-Party PCIe AnalyzerA third-party logic analyzer for PCI Express records the traffic on the physical link and decodes traffic,saving you the

Frequently Asked QuestionsA2015.05.04UG-01145_avstSubscribeSend FeedbackThe following miscellaneous facts might be of assistance in troubleshooting:•

Lane Initialization and ReversalB2015.05.04UG-01145_avstSubscribeSend FeedbackConnected components that include IP blocks for PCI Express need not sup

Figure B-1: Using Lane Reversal to Solve PCB Routing ProblemsThe following figure illustrates a PCI Express card with ×4 IP Root Port and a ×4 Endpoin

Additional InformationC2015.05.04UG-01145_avstSubscribeSend FeedbackRevision History for the Avalon-ST InterfaceDate Version Changes Made2015.05.04 15

Date Version Changes Made• Corrected width of rx_st_sop and rx_st_eop to 1 or two bits. Ifyou turn on Enable multiple packets per cycle these signals

Date Version Changes MadeMade the following changes to the user guide:• Added statement that the bottom left hard IP block includes theCvP functionali

Figure 2-4: Testbench for PCI ExpressHard IP for PCI ExpressAltera FPGAPCBRoot Port BFM perstn (npor)ResetAPPS DUTChaining DMA (User Application) Tran

Date Version Changes Made• Removed txdatavalid0 signal from the PIPE interface. Thissignal is not available.• Removed references to the MegaWizard® Pl

Date Version Changes Made2013.12.20 13.1 Made the following changes:• Divided user guide into 3 separate documents by interface type.• Added Design Im

Date Version Changes Made2013.05.06 13.0 • Added support for Configuration Space Bypass Mode, allowingyou to design a custom Configuration Space and s

Contact (1)Contact Method AddressTechnical support Website www.altera.com/supportTechnical trainingWebsite www.altera.com/trainingEmail custrain@alte

Visual Cue Meaningitalic type Indicates variables. For example, n + 1.Variable names are enclosed in angle brackets (< >).For example, <file

Visual Cue Meaningm The multimedia icon directs you to a relatedmultimedia presentation.c A caution calls attention to a condition or possiblesituatio

Files Generated for Altera IP CoresThe Quartus II software generates the following IP core output file structure:Figure 2-5: IP Core Generated Files&l

File Name Description<system>.sopcinfo Describes the connections and IP component parameterizations inyour Qsys system. You can parse its conten

Parameter Settings... 4-1System Settings ...

File Name Description<my_ip>.regmap If the IP contains register information, the .regmap file generates.The .regmap file describes the register

Getting Started with the Configuration SpaceBypass Mode Qsys Example Design32014.08.18UG-01145_avstSubscribeSend FeedbackThis Qsys design example demo

Figure 3-1: Configuration Bypass Mode Qsys Example Design to PCIe Root Portand Host SystemConfigurationBypass Top(cfbp_top)APPS: Config Bypass Exa

Figure 3-2: Configuration Bypass Qsys System1. Note the following parameter settings for the Configuration Space Bypass Example Design:• For the DUT,

Table 3-1: Parameters to Specify on the Generation Tab in QsysParameter ValueCreate testbench Qsys system Standard, BFMs for standard Avalon interface

Understanding Simulation Log File GenerationStarting with the Quartus II 14.0 software release, simulation automatically creates a log file, altpcie_m

1. To observe the simulation, on the ModelSim View menu, select wave. Then add some key interfaces tothe wave window. The following four interfaces un

Figure 3-4: Configuration Read to Function 0RxStMask_oRxStSop_iRxStEop_iRxStValid_iRxStReady_oRxStData_i[255:0]cfg_addr_o[31:0]cfg_rden_ocfg_wren_ocfg

The preceding timing diagram illustrates the following sequence of events:1. The Application Layer indicates it is ready to receive requests by assert

Figure 3-5: Configuration Write to Function 0RxStMask_oRxStSop_iRxStEop_iRxStValid_iRxStReady_oRxStData_i[255:0cfg_addr_o[31:0]cfg_rden_ocfg_wren_cfg_

Hard IP Reconfiguration Interface ...6-52Power M

Figure 3-6: Timing for Memory Write and Read of Function 1RxStMask_oRxStSop_iRxStEop_iRxStValid_iRxStReady_oTxStReady_iTxStSop_oTxStEop_oTxStValid_ or

The timing diagram illustrates the following sequence of events:1. The Application Layer indicates it is ready to receive requests by asserting RxSTRe

# INFO: 48089 ns RP LTSSM State: L0 # INFO: 48133 ns EP LTSSM State: L0 # INFO: 48226 ns Configuring Bus 000, Device 000, Function 00 # INFO: 48226 ns

# INFO: 73354 ns TASK:my_test Memory write burst at addr=0x08# with wdata=0x10203040 # INFO: 73362 ns TASK:my_test => 2.21 Memory Read burst# INF

Parameter Settings42014.08.18UG-01145_avstSubscribeSend FeedbackSystem SettingsTable 4-1: System Settings for PCI ExpressParameter Value DescriptionNu

Parameter Value Descriptionperformancefor receivedrequestsHighMaximumallow you to adjust the credit allocation to optimize your system.The credit allo

Parameter Value Description• Minimum—configures the minimum PCIe specificationallowed for non-posted and posted request credits, leaving mostof the RX

Parameter Value DescriptionEnable byteparity ports onAvalon-STinterfaceOn/Off When On, the RX and TX datapaths are parity protected. Parity isodd.This

Parameter Value DescriptionEnable AlteraDebug MasterEndpoint(ADME)On/OffWhen On, you can use the Altera System Console to read and writethe embedded A

Table 4-3: BAR RegistersParameter Value DescriptionType Disabled64-bit prefetchable memory32-bit non-prefetchable memory32-bit prefetchable memoryI/O

Interrupts ... 11-

Base and Limit Registers for Root PortsTable 4-4: Base and Limit RegistersThe following table describes the Base and Limit registers which are availab

Register Name Range Default Value DescriptionRevision ID 8 bits 0x00000000 Sets the read-only value of the Revision ID register.Address offset: 0x008.

Device CapabilitiesTable 4-6: Capabilities RegistersParameter Possible Values Default Value DescriptionMaximumpayload size128 bytes256 bytes512 bytes1

Parameter Possible Values Default Value Descriptionfunctions this field is reserved and must be hardwired to0x0000b. Four time value ranges are define

Parameter Value Default Value DescriptionEnableECRCcheckingOn/Off Off When On, enables ECRC checking. Sets the read-onlyvalue of the ECRC check capabl

Parameter Value DescriptionData link layeractive reportingOn/OffTurn On this parameter for a downstream port, if thecomponent supports the optional ca

Parameter Value DescriptionTable Offset [31:0] Points to the base of the MSI-X Table. The lower 3 bits of thetable BAR indicator (BIR) are set to zero

Parameter Value DescriptionSlot power scale0–3Specifies the scale used for the Slot power limit. The followingcoefficients are defined:• 0 = 1.0x• 1 =

Parameter Value DescriptionEndpoint L1acceptablelatencyMaximum of 1 usMaximum of 2 usMaximum of 4 usMaximum of 8 usMaximum of 16 usMaximum of 32 usNo

Physical Layout of Hard IP In Arria 10 Devices52015.05.04UG-01145_avstSubscribeSend FeedbackArria 10 devices include 1–4 hard IP blocks for PCI Expres

Chaining DMA Control and Status Registers ...17-9Chaining DMA Descriptor Table

Figure 5-2: Arria 10 Devices with 72 Transceiver Channels and Four PCIe Hard IP BlocksTransceiverBankTransceiverBankTransceiverBankTransceiverBankTran

Figure 5-3: Arria 10 GT Devices with 48 Transceiver Channels and Two PCIe Hard IP BlocksTransceiverBankTransceiverBankTransceiverBankTransceiverBankTr

Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data RatesThe following figures illustrate the x1, x2, x4, and x8 channel and pin placements fo

Figure 5-6: Arria 10 Gen1, Gen2, and Gen3 x4 Channel and Pin PlacementPMA Channel 5PMA Channel 4PMA Channel 3PMA Channel 0PMA Channel 3PMA Channel 2

Figure 5-8: Arria 10 Gen1 and Gen2 x1 Channel PlacementPMA Channel 5PMA Channel 4PMA Channel 3PMA Channel 2PMA Channel 0PMA Channel 3PMA Channel 2PM

Figure 5-11: Gen1 and Gen2 x8 Channel PlacementPMA Channel 5PMA Channel 4PMA Channel 3PMA Channel 0PMA Channel 3PMA Channel 2PMA Channel 1PMA Channe

Figure 5-13: Arria 10 Gen3 x2 Channel PlacementPMA Channel 5PMA Channel 4PMA Channel 3PMA Channel 0PMA Channel 4PMA Channel 3PMA Channel 2PMA Channe

Interfaces and Signal Descriptions62015.05.04UG-01145_avstSubscribeSend FeedbackFigure 6-1: Avalon-ST Hard IP for PCI Express Top-Level Signalsrx_st_d

Avalon‑ST RX InterfaceThe following table describes the signals that comprise the Avalon-ST RX Datapath. The RX data signalcan be 64, 128, or 256 bits

Signal Direction DescriptionFor 128-bit data, only bit 0 applies; this bit indicates whether theupper qword contains data. For 256-bit data single pac

Revision History for the Avalon-ST Interface...C-1How to Contact

Signal Direction Descriptionrx_st_valid Output Clocks rx_st_data into the Application Layer. Deasserts within2 clocks of rx_st_ready deassertion and

Signal Direction Descriptionrx_st_bar[7:0] Output The decoded BAR bits for the TLP. Valid for MRd, MWr, IOWR, andIORD TLPs. Ignored for the completion

Signal Direction Descriptionrx_st_be[<n>-1:0] Output Byte enables corresponding to the rx_st_data. The byte enablesignals only apply to PCI Expr

Qword alignment applies to all types of request TLPs with data, including the following TLPs:• Memory writes• Configuration writes• I/O writesThe alig

Packet TLPData<n> pcie_data_byte<4n+3>, pcie_data_byte<4n+2>, pcie_data_byte<4n+1>, pcie_data_byte<n>The following figur

Figure 6-5: 64-Bit Avalon-ST rx_st_data<n> Cycle Definitions for 4-Dword Header TLPs with QwordAligned AddressesThe following figure shows the m

Figure 6-7: 64-Bit Application Layer Backpressures Transaction LayerThe following figure illustrates the timing of the RX interface when the Applicati

Data Alignment and Timing for the 128‑Bit Avalon‑ST RX InterfaceFigure 6-9: 128-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header

Figure 6-10: 128-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with non-Qword Aligned AddressesThe following figure shows

Figure 6-12: 128-Bit Avalon-ST rx_st_data Cycle Definition for 4-Dword Header TLPs with QwordAligned AddressesThe following figure shows the mapping o

Datasheet12015.05.04UG-01145_avstSubscribeSend FeedbackArria 10 Avalon-ST Interface for PCIe DatasheetAltera® Arria® 10 FPGAs include a configurable,

Figure 6-14: 128-Bit Avalon-ST Interface Back-to-Back TransmissionThe following figure illustrates back-to-back transmission on the 128-bit Avalon-ST

Data Alignment and Timing for 256‑Bit Avalon‑ST RX InterfaceFigure 6-16: Location of Headers and Data for Avalon-ST 256-Bit InterfaceThe following fig

The smallest PCIe packet, such as a 3-dword memory read, uses 96 bits of the 256-bits bus and achieve thefollowing throughput:96/256*8 = 3 GBytes/secI

Table 6-4: 64-, 128-, or 256‑Bit Avalon-ST TX DatapathSignal Direction Descriptiontx_st_data[<n>-1:0]Input Data for transmission. Transmit data

Signal Direction Descriptiontx_st_ready Output Indicates that the Transaction Layer is ready to accept data fortransmission. The core deasserts this s

Signal Direction Descriptionwords that contain data, resulting in the following encodings forthe 128-and 256-bit interfaces:128-Bit interface:tx_st_em

Signal Direction Descriptiontx_st_errInput Indicates an error on transmitted TLP. This signal is used tonullify a packet. It should only be applied to

Signal Direction Descriptiontx_cred_fc_hip_cons[5:0]Output Asserted for 1 cycle each time the Hard IP consumes a credit.These credits are from message

Signal Direction Descriptionko_cpl_spc_header[7:0]Output The Application Layer can use this signal to build circuitry toprevent RX buffer overflow for

Figure 6-19: 64-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with Non-QwordAligned Addresspld_clktx_st_data[63:32]tx_st_data[31:0]

Link Width×1 ×2 ×4 ×8PCI Express Gen3(8.0 Gbps)7.87 15.75 31.51 63Refer to the AN 456: PCI Express High Performance Reference Design for more informat

Figure 6-21: 64-Bit Avalon-ST tx_st_data Cycle Definition for TLP 4-Dword Header with Non-QwordAligned Addresspld_clktx_st_data[63:32]tx_st_data[31:0]

Figure 6-23: 64-Bit Back-to-Back Transmission on the TX InterfaceThe following figure illustrates back-to-back transmission of 64-bit packets with no

Figure 6-25: 128-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with non-QwordAligned AddressThe following figure shows the mapping

Header 3 Data 2Header 2 Data 1Data nHeader 1 Data 0Data n-1Header 0Data n-2pld_clktx_st_validtx_st_data[127:96]tx_st_data[95:64]tx_st_data[63:32]tx_st

pld_clktx_st_data[127:0]tx_st_soptx_st_eoptx_st_emptytx_st_readytx_st_validtx_st_err000 CC... CC... CC... CC... CC... CC... CC... CC... CC... CC... CC

Figure 6-30: 256-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with QwordAddressesThe following figure illustrates the layout of he

Figure 6-31: 256-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with QwordAddresses01 10clktx_st_data[63:0]Aligned Data Unaligned Da

Related InformationTradeoffs to Consider when Enabling Multiple Packets per Cycle on page 6-15Root Port Mode Configuration RequestsIf your Application

Table 6-6: Reset SignalsSignal Direction DescriptionnporInput Active low reset signal. In the Altera hardware example designs,npor is the OR of pin_pe

Signal Direction DescriptionRefer to the appropriate device pinout for correct pin assignmentfor more detailed information about these pins. The PCI E