Altera MAX 10 Embedded Memory Bedienungsanleitung PDF herunterladen (Seite 37)

Signal Required Description

rden_a Optional Read enable input for address_a port. The rden_a port is

supported depending on your selected memory mode and

memory block.

rden_b Optional Read enable input for address_b port. The rden_b port is

supported depending on your selected memory mode and

memory block.

byteena_a Byte enable input to mask the data_a port so that only specific

bytes, nibbles, or bits of the data are written. The byteena_a

port is not supported in the following conditions:

• If the implement_in_les parameter is set to ON.

• If the operation_mode parameter is set to ROM.

addressstall_a Optional Address clock enable input to hold the previous address of

address_a port for as long as the addressstall_a port is high.

addressstall_b Optional Address clock enable input to hold the previous address of

address_b port for as long as the addressstall_b port is high.

Table 5-4: RAM:2-Port IP Core Output Signals (True Dual-Port RAM)

Signal Required Description

q_a Yes Data output from Port A of the memory. The q_a port is

required if the operation_mode parameter is set to any of the

following values:

• SINGLE_PORT

• BIDIR_DUAL_PORT

• ROM

The width of q_a port must be equal to the width of data_a

port.

q_b Yes Data output from Port B of the memory. The q_b port is

required if you set the operation_mode to the following values:

• DUAL_PORT

• BIDIR_DUAL_PORT

The width of q_b port must be equal to the width of data_b

port.

RAM: 2-Port IP Core Parameters for MAX 10 Devices

Table 5-5: RAM: 2-Port IP Core Parameters for MAX 10 Devices

This table lists the IP core parameters applicable to MAX 10 devices.

Option Legal Values Description

Parameter Settings: General

UG-M10MEMORY

2015.05.04

RAM: 2-Port IP Core Parameters for MAX 10 Devices

5-9

RAM: 2-PORT IP Core References

Altera Corporation

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