Altera MAX 10 Embedded Memory Bedienungsanleitung Seite 5
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MAX 10 Embedded Memory Architecture and
Features
2
2015.05.04
UG-M10MEMORY
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The MAX 10 embedded memory structure consists of 9,216-bit (including parity bits) blocks. You can use
each M9K block in different widths and configuration to provide various memory functions such as
RAM, ROM, shift registers, and FIFO.
The following list summarizes the MAX 10 embedded memory features:
• Embedded memory general features
• Embedded memory operation modes
• Embedded memory clock modes
Related Information
MAX 10 Device Overview
For information about MAX 10 devices embedded memory capacity and distribution
MAX 10 Embedded Memory General Features
MAX 10 embedded memory supports the following general features:
• 8,192 memory bits per block (9,216 bits per block including parity).
• Independent read-enable (rden) and write-enable (wren) signals for each port.
• Packed mode in which the M9K memory block is split into two 4.5 K single-port RAMs.
• Variable port configurations.
• Single-port and simple dual-port modes support for all port widths.
• True dual-port (one read and one write, two reads, or two writes) operation.
• Byte enables for data input masking during writes.
• Two clock-enable control signals for each port (port A and port B).
• Initialization file to preload memory content in RAM and ROM modes.
Control Signals
The clock-enable control signal controls the clock entering the input and output registers and the entire
M9K memory block. This signal disables the clock so that the M9K memory block does not see any clock
edges and does not perform any operations.
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101 Innovation Drive, San Jose, CA 95134
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Subscribe 4
- Features 5
- Parity Bit 6
- Read Enable 6
- Read-During-Write 7
- Byte Enable 7
- Packed Mode Support 8
- Address Clock Enable Support 9
- Asynchronous Clear 10
- Related Information 11
- Altera Corporation 12
- Send Feedback 12
- UG-M10MEMORY 13
- 2015.05.04 13
- Port Width Configurations 14
- Read Port 16
- Write Port 16
- Memory Block Valid Range 16
- MAX 10 Embedded Memory Design 17
- Consideration 17
- A B C D E F 18
- A B C D E 18
- If You... ...Then 20
- Signal Required Description 24
- Parameter Values Description 25
- Options Enabled 29
- Option Enabled 53
- Option Values Description 61
- FIFO IP Core References 62
- LPM_WIDTHU 66
- ALTMEMMULT IP Core References 69
- Memory User Guide 71
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