Altera CPRI v6.0 MegaCore Function Bedienungsanleitung Seite 82
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CPRI v6.0 IP Core Signals
4
2014.08.18
UG-01156
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The CPRI v6.0 IP core communicates with the surrounding design through multiple external signals.
Many of the signal interfaces are optional; their presence or absence depends on whether or not you
enable the corresponding interface in the CPRI v6.0 parameter editor.
In the case of the interfaces that provide direct access to all or part of the CPRI frame, write transmit delay
relative to the AUX TX interface synchronization signals depends on the Auxiliary latency cycle(s)
parameter setting.
CPRI v6.0 IP Core L2 Interface
The CPRI v6.0 IP core optionally communicates with an user-provided Ethernet MAC through the
following signals.
Table 4-1: MII Signals
Signal Name Direction Interface
mii_rxclk Input
RX MII signals
These signals are available only if you turn on Enable
IEEE 802.3 100BASE-X 100Mbps MII in the CPRI v6.0
parameter editor.
mii_rxreset Input
mii_rxdv Output
mii_rxer Output
mii_rxd[3:0] Output
mii_txclk Input
TX MII signals
These signals are available only if you turn on Enable
IEEE 802.3 100BASE-X 100Mbps MII in the CPRI v6.0
parameter editor.
mii_txreset Input
mii_txen Input
mii_txer Input
mii_txd[3:0] Input
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101 Innovation Drive, San Jose, CA 95134
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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