Altera CPRI v6.0 MegaCore Function Bedienungsanleitung Seite 78
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Signal Name Direction Description
xcvr_tx_cal_busy
Output Indicates to external reset controller that the transmitter is
still busy with the calibration process.
xcvr_rx_analogreset
Input Analog reset to receiver from external reset controller.
xcvr_rx_digitalreset
Input Digital reset to receiver from external reset controller.
xcvr_rx_cal_busy
Output Indicates to external reset controller that the receiver is still
busy with the calibration process.
xcvr_reset_tx_ready
Input
Indicates the Tx reset controller reset sequence is
completed. When this signal is asserted, the IP core begins a
reset of the IP core Tx path.
xcvr_reset_rx_ready
Input
Indicates the Rx reset controller reset sequence is
completed. When this signal is asserted, the IP core begins a
reset of the IP core Rx path.
Related Information
Adding the External Reset Controller on page 2-14
Altera Transceiver PHY IP Core User Guide
Information about the Altera Transceiver Reset Controller IP core for Arria V GZ and Stratix V devices.
Arria 10 Transceiver PHY User Guide
Information about the Altera Transceiver Reset Controller IP core for Arria 10 devices.
Interface to the External PLL
Table 3-27: CPRI v6.0 IP Core External PLL Interface Signals
The CPRI v6.0 IP core requires that you generate and connect an external transceiver PLL IP core.
Signal Name Direction Description
xcvr_ext_pll_clk Input
Clocks the transmitter PMA.
You should drive this input clock with the output of the
external transceiver TX PLL. In Arria 10 devices, you have a
choice of different TX PLL IP cores to configure. You must
ensure that you configure a PLL IP core that is capable of
driving the frequency that the CPRI v6.0 IP core requires to
run at the specified CPRI line bit rate.
Related Information
Adding the External TX PLL on page 2-13
Altera Transceiver PHY IP Core User Guide
Information about the Arria V GZ and Stratix V transceiver PLL IP cores.
Arria 10 Transceiver PHY User Guide
Information about the Arria 10 transceiver PLL IP cores.
3-48
Interface to the External PLL
UG-01156
2014.08.18
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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