Altera CPRI v6.0 MegaCore Function Bedienungsanleitung Seite 39
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Figure 3-4: Start-Up Sequence State Machine Timing Diagram
000 111 110 101001 011
000
001
011 111 110
cpri_clkout
state_startup_sequence
state_l1_sync
nego_bitrate_complete
nego_vss_complete
Bit Rate
Negotiation
Protocol Version
Negotiation
Control and Management Rate
Negotiation
VSS and Interface
Negotiation
Operational
Mode
AUX Interface
The CPRI v6.0 IP core auxiliary (AUX) interface provides direct access to the CPRI 10 ms radio frame,
including I/Q data and control words. You can use this interface to support your specific application. For
example, the AUX interface allows you to implement custom I/Q sample widths and custom mapping
schemes.
The AUX interface also enables multi-hop routing applications and provides timing reference informa‐
tion for transmitted and received frames. Using this interface, you can load I/Q data in a precise location
in the precise CPRI basic frame you target.
The AUX interface allows you to connect CPRI v6.0 IP core instances and other system components
together by supporting a direct connection to a user-defined routing layer or custom mapping block. You
implement this routing layer, which is not defined in the CPRI V6.0 Specification, outside the CPRI v6.0
IP core. The AUX interface supports the transmission and reception of I/Q data and timing information
between an RE slave and an RE master, allowing you to define a custom routing layer that enables daisy-
chain configurations of RE master and slave ports. Your custom routing layer determines the I/Q sample
data to pass on to other REs to support multi-hop network configurations and custom mapping
algorithms.
If you turn on Enable auxiliary interface in the CPRI v6.0 parameter editor, your IP core includes this
interface.
UG-01156
2014.08.18
AUX Interface
3-9
Functional Description
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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