Altera CPRI v6.0 MegaCore Function Bedienungsanleitung Seite 101
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Table 5-15: CPRI v6.0 IP Core CTRL_INDEX Register at Offset 0x30
Frequency differences between the control and status interface clock cpu_clk and the main CPRI v6.0 IP core
clock cpri_clkout might cause non-zero read latency and more than one clock cycle of write latency when
accessing this register.
Bits Field Name Type Value on
Reset
Description
31:27 Reserved UR0 5'b0
26:24 rx_ctrl_
seq
RW 3'b0 Sequence number for CPRI control word 32-bit section
monitoring. The value in this field determines the 32-bit
section of the control receive table entry that appears in the RX_
CTRL register. The value indicates whether this is the first,
second, third, fourth, or fifth (for RTVS) 32-bit section in the
control word.
23:16 rx_ctrl_x RW 8'b0 Index for CPRI control word monitoring (X value in frame
location #Z.X.Y). The value in this field determines the control
receive table entry of which a 32-bit section appears in the RX_
CTRL register.
15:12 Reserved UR0 4'b0
11 tx_ctrl_
insert
RW 1'b0 Control word 32-bit section transmit enable. This value is
stored in the control transmit table with its associated entry.
When you change the value of the tx_ctrl_seq field or the tx_
ctrl_x field, the stored tx_ctrl_insert bit associated with
the indexed entry appears in the tx_ctrl_insert field.
At the time the CPRI v6.0 IP core can insert a control transmit
table entry in the associated position in the outgoing
hyperframe on the CPRI link, if the tx_ctrl_insert bit
associated with that entry has the value of 1, and the tx_ctrl_
insert_en bit of the L1_CONFIG register is asserted, the IP core
inserts the table entry in the hyperframe.
10:8 RW 3'b0 Sequence number for CPRI control word 32-bit section
insertion. The value in this field determines the 32-bit section
of the control transmit table entry that appears in the TX_CTRL
register. The value indicates whether this is the first, second,
third, fourth, or fifth (for RTVS) 32-bit section in the control
word.
7:0 RW 8'b0 Index for CPRI control word insertion (X value in frame
location #Z.X.Y). The value in this field determines the control
transmit table entry of which a 32-bit section appears in the TX_
CTRL register.
TX_CTRL Register
5-12
TX_CTRL Register
UG-01156
2015.02.16
Altera Corporation
CPRI v6.0 IP Core Registers
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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