Altera CPRI v6.0 MegaCore Function Bedienungsanleitung Seite 76
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Main Transceiver Clock and Reset Signals
Table 3-23: Main Transceiver Clock and Reset-Done Signals
The clocks for individual interfaces are listed with the relevant interface signals.
Signal Name Direction Description
xcvr_cdr_refclk Input Receiver CDR reference clock. You must drive this clock
at the frequency you specified for the Supported receiver
CDR frequency (MHz) parameter in the CPRI v6.0
parameter editor.
xcvr_recovered_clk Output Direct recovered clock from the receiver CDR. Use this
output clock to drive the external clean-up PLL when your
IP core is in slave mode.
xcvr_reset_tx_done Output Indicates the transmitter and IP core Tx path have
completed the internal reset sequence. This signal is
clocked by the cpri_clkout clock.
xcvr_reset_rx_done Output Indicates the receiver and IP core Rx path have completed
the internal reset sequence. This signal is clocked by the
cpri_clkout clock.
Arria V GZ and Stratix V Transceiver Reconfiguration Interface
Table 3-24: Arria V GZ and Stratix V Transceiver Reconfiguration Interface Signals
All interface signals are clocked by the reconfig_clk clock.
Signal Name Direction Description
reconfig_clk Input Clock for CPRI v6.0 IP core transceiver start-up and
reconfiguration. The frequency range for this clock is 100–
150 MHz.
reconfig_to_xcvr[69:0] Input Parallel transceiver reconfiguration bus from the Altera
Transceiver Reconfiguration Controller to the transceiver
in the CPRI v6.0 IP core.
reconfig_from_xcvr[45:0] Output Parallel transceiver reconfiguration bus to the Altera
Transceiver Reconfiguration Controller from the
transceiver in the CPRI v6.0 IP core.
Related Information
Adding the Transceiver Reconfiguration Controller on page 2-15
Altera Transceiver PHY IP Core User Guide
Information about the Transceiver Reconfiguration Controller IP core.
Arria 10 Transceiver Reconfiguration Interface
Altera provides a dedicated Avalon-MM interface, called the Arria 10 transceiver reconfiguration
interface, to access the Arria 10 transceiver registers. You access the Arria 10 Native PHY IP core registers
through this dedicated interface and not through the IP core general purpose control and status interface.
This interface provides access to the hard PCS registers on the device.
3-46
Main Transceiver Clock and Reset Signals
UG-01156
2014.08.18
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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