Altera CPRI v6.0 MegaCore Function Bedienungsanleitung Seite 29
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Parameter Value
Operation mode Master
Supported receiver CDR frequency (MHz) 307.2
Receiver FIFO depth (value shown is log2 of actual
depth)
6
Enable auto-rate negotiation Turn off
Enable auto-rate negotiation down to 614.4Mbps Not available
Supported CPU interface standard AvalonMM
Auxiliary latency cycle(s) 0
Enable auxiliary interface Turn on
Enable all control word access Turn off
Enable direct IQ mapping interface Turn off
Enable direct ctrl_axc access interface Turn on
Enable direct vendor specific access interface Turn on
Enable start-up sequence state machine Turn off
Enable L1 inband protocol negotiator Not available
Enable real-time vendor specific interface (R-16A) Not available
Enable Z.130.0 access interface Turn off
Enable direct HDLC serial interface Turn on
Enable IEEE 802.3 100BASE-X 100Mbps MII Turn on
L2 Ethernet PCS Tx/Rx FIFO depth (value shown is
log2 of actual depth)
Turn off
Enable debug interface Turn off
Enable transceiver PMA forward loopback path (Tx
to Rx)
Turn off
Enable forward loopback path (Tx to Rx) Turn off
Enable reversed loopback path (Rx to Tx) Turn off
4. In the CPRI v6.0 parameter editor, click the Example Design button and specify the desired location
of the testbench.
5. After you generate the demonstration testbench, in the Quartus II software, click View > Utility
Windows > Tcl Console.
6. In the Tcl Console, change directory to your specified testbench directory's ip_sim subdirectory.
7. Type source gen_sim_verilog.tcl or source gen_sim_vhdl.tcl, depending on the language of
the model you wish to simulate. Running this script generates the DUT and testbench files.
8. If you are using a simulator that requires that you open a user interface, open your target simulator.
2-18
Running the Testbench
UG-01156
2014.08.18
Altera Corporation
Getting Started with the CPRI v6.0 IP Core
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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