Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Bedienungsanleitung PDF herunterladen (Seite 99)

to 644.53125 MHz ±100 ppm. For 24.24 Gbps variations, you must set the frequency of clk_ref either to

390.625 MHz ±100 ppm or to 195.3125 MHz ±100 ppm.

Sync–E IP core variations are duplex IP core variations for which you turn on Enable SyncE support in

the parameter editor. These variations provide separate IP core input reference clock signals for the TX

and RX transceiver PLLs, and provide the RX recovered clock as a top-level output signal.

The Synchronous Ethernet standard, described in the ITU-T G.8261, G.8262, and G.8264 recommenda‐

tions, requires that the TX clock be filtered to maintain synchronization with the RX reference clock

through a sequence of nodes. The expected usage is that user logic drives the tx_ref_clk signal with a

filtered version of the RX recovered clock signal, to ensure the receive and transmit functions remain

synchronized.

In a Sync–E IP core, the restrictions apply to each of the rx_clk_ref and tx_clk_ref input clocks.

The minimum clock frequency for the IP core is 315 MHz. The only exception is the 40GbE lower rate

24.24 Gbps MAC and PHY IP core, which has a minimum clock frequency of 190.90 MHz.

Table 3-16: Clock Inputs

Describes the input clocks that you must provide.

Signal Name Description

clk_status A clock for reconfiguration, offset cancellation, and housekeeping

functions. This clock is also used for clocking the control and status

interface. The clock quality and pin chosen are not critical. clk_status is

expected to be a 37.5–50 MHz clock on Stratix IV devices and a 100–

125 MHz clock on Stratix V devices.

clk_ref clk_ref is the reference clock for the transceiver TX PLL and the RX

CDR PLL. This input signal is not available in Sync–E variations.

The frequency of this input clock must match the value you specify for

PHY reference frequency in the IP core parameter editor.

For the regular 40GbE and 100GbE IP core variations, this clock must

have a frequency of 322.265625 or 644.53125 MHz with a ±100 ppm

accuracy per the IEEE 802.3ba-2010 100G Ethernet Standard.

Despite its apparent availability in the 40-100GbE parameter editor,

CAUI–4 variations do not support the 322 MHz clock frequency. For

these variations, this clock must have a frequency of 644.53125 MHz with

a ±100 ppm accuracy.

For 24.24 Gbps IP core variations, this clock must have a frequency of

390.625 or 195.3125 MHz with a ±100 ppm accuracy.

In addition, clk_ref must meet the jitter specification of the IEEE

802.3ba-2010 100G Ethernet Standard.

The PLL and clock generation logic use this reference clock to derive the

transceiver and PCS clocks. The input clock should be a high quality

signal on the appropriate dedicated clock pin.

The PCS clock frequency is 257.8125 MHz for standard variations,

201.416 MHz for CAUI–4 variations, and 156.25 MHz for 24.24 Gbps

variations.

3-52

Clocks

UG-01088

2014.12.15

Altera Corporation

Functional Description

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