Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Bedienungsanleitung Seite 92
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align_status is true and the scrambled idle RX test-pattern mode is active, the scrambled idle test-
pattern checker observes the synchronous header and the output from the descrambler. When the
synchronous header and the output of the descrambler is an idle pattern, a match is detected. When
operating in scrambled idle test pattern, the test-pattern error counter counts blocks with a mismatch.
Any mismatch indicates an error and shall increment the test-pattern error counter.
The test-pattern check uses the following register fields:
1. Bit 1 of the TEST_MODE register at offset 0x019 enables the RX test-pattern mode.
2. The TEST_PATTERN_COUNTER register at offset 0x01A , a 32-bit register that saturates, counts the
number of mismatched blocks when the IP core is in test-pattern mode.
3. Bit 2 of the TEST_MODE register enables software to clear the test-pattern error counter.
Related Information
• Test Mode Register on page 3-88
Information about the TEST_MODE register.
• Test Pattern Counter Register on page 3-88
Information about the TEST_PATTERN_COUNTER register.
• IEEE website
The IEEE 802.3ba-2010 100G Ethernet Standard is available on the IEEE website.
Transceiver PHY Serial Data Interface
The core uses a 40-bit ×<n> lane digital interface to send data to the TX high-speed serial I/O pins
operating at 10.3125 Gbps in the standard 40GbE and 100GbE variations, at 6.25 Gbps in the 24.24
variations, and at 25.78125 Gbps in the CAUI–4 variations. The rx_serial and tx_serial ports connect
to the 10.3125 Gbps, 6.25 Gbps, or 25.78125 Gbps pins. The protocol includes automatic reordering of
serial lanes so that any ordering is acceptable. Virtual lanes 0 and 1 transmit data on tx_serial[0].
PCS BER Monitor
The PCS implements bit error rate (BER) monitoring as specified by the IEEE 802.3ba-2010 100G
Ethernet Standard. When the PCS deskews the data and aligns the lanes, the BER monitor checks the
signal quality and asserts hi_ber if it detects excessive errors. When align_status is asserted and hi_ber
is deasserted, the RX PCS continuously accepts blocks and generates RXD <63:0> and RXC <7:0> on the
XLGMII or CGMII interface.
High BER occurs when 97 invalid 66-bit synchronous headers are detected for 100GbE within 500 µs or
detected for 40GbE within 1.25 ms. When fewer than 97 invalid 66-bit synchronous headers occur in the
same window, the IP core exists the high BER state.
For more information, refer to Figure 82–13—BER monitor state diagram illustrated in the IEEE
802.3ba-2010 100G Ethernet Standard.
Related Information
IEEE website
The IEEE 802.3ba-2010 100G Ethernet Standard is available on the IEEE website.
UG-01088
2014.12.15
Transceiver PHY Serial Data Interface
3-45
Functional Description
Altera Corporation
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- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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