Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Bedienungsanleitung Seite 57
- Seite / 199
- Inhaltsverzeichnis
- LESEZEICHEN
Bewertet. / 5. Basierend auf Kundenbewertungen
Table 3-3: Signals of the TX Client Interface Without Adapters
In the table, <w> = 2 for the 40GbE IP core and <w> = 5 for the 100GbE IP core.
Signal Name Direction Description
din[<w>*64-1:0]
Input Data bytes to send in big-Endian mode.
din_start[<w>-
1:0]
Input Start of packet (SOP) location in the TX data bus. Only the most
significant byte of each 64-bit word may be a start of packet. Bit 63 or
127 are possible for the 40GbE and bits 319, 255, 191, 127, or 63 are
possible for 100 GbE.
din_end_pos[<w>
*8-1:0]
Input End of packet. Any byte may be the last byte in a packet.
din_ack Output Indicates that input data was accepted by the IP core.
clk_txmac Input TX MAC clock. The minimum clock frequency is 315 MHz for the
circuit to function correctly. The clk_txmac and clk_rxmac which
clocks the RX datapath are not related and their rates do not have to
match.
The IP core reads the bytes in big endian order. A packet may start in the most significant byte of any
word. A packet may end on any byte.
To avoid sending packets before the IP core completes the reset sequence, you should ensure that the
application does not send packets on the TX client interface until after the lanes_deskewed signal is
asserted.
Related Information
• 40GbE IP Core Without Adapters on page 3-12
Illustrates the 40GbE IP core TX client interface without adapters.
• 100GbE IP Core Without Adapters on page 3-14
Illustrates the 100GbE IP core TX client interface without adapters.
Bus Quantization Effects With Adapters
The TX custom streaming interface allows a packet to start at any of two or five positions to maximize
utilization of the link bandwidth. The TX Avalon-ST interface only allows start of packet (SOP) to be
placed at the most significant position. If the SOP were restricted to the most significant position in the
client logic data bus in the custom streaming interface, bus bandwidth would be reduced.
3-10
Bus Quantization Effects With Adapters
UG-01088
2014.12.15
Altera Corporation
Functional Description
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
Verwandte Produkte und Handbücher für Messgeräte Altera 40-Gbps Ethernet MAC and PHY MegaCore Function
Messgeräte Altera PHYLite Bedienungsanleitung
(61 Seiten)
(61 Seiten)
Messgeräte Altera Arria GX Bedienungsanleitung
(32 Seiten)
(32 Seiten)
Messgeräte Altera Arria V GX Bedienungsanleitung
(52 Seiten)
(52 Seiten)
© 2020, manymanuals.de. Alle Rechte vorbehalten. | 0.024 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Kommentare zu diesen Handbüchern