Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Bedienungsanleitung Seite 31
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Parameter Type Range Default
Setting
Parameter Description
Include FEC
sublayer
Boolean • True
• False
False If this parameter is turned on, the IP core includes
logic to implement FEC.
Set FEC_ability
bit on power
up/reset
Boolean • True
• False
True
If this parameter is turned on, the IP core sets the
FEC ability bit (40GBASE-KR4 register offset 0xB0,
bit 16) on power up and reset.
Set FEC_Enable
bit on power
up/reset
Boolean • True
• False
True
If this parameter is turned on, the IP core sets the
FEC enable bit (40GBASE-KR4 register offset 0xB0,
bit 18) on power up and reset. If you turn on this
parameter but do not turn on Set FEC_ability bit on
power up/reset, this parameter has no effect: the IP
core cannot specify the value of 1 for FEC Requested
without specifying the value of 1 for FEC Ability.
Set FEC_Error_
indication_
ability bit on
power up/reset
Boolean • True
• False
True
If this parameter is turned on, the IP core is
programmed by default (40GBASE-KR4 register
offset 0xB0, bit 17) to report decoding errors to the
PCS.
Use M20K for
FEC Buffer (if
available)
Boolean • True
• False
True
If this parameter is turned on, the IP core is
configured with a pipelined FEC buffer to support the
Quartus II software in inferring M20K memory.
Turning on this parameter potentially saves device
resources.
Table 2-3: 40-100GbE PHY Parameter Settings
Lists the PHY parameters that are configured automatically based on parameter values you select in the 40G/100G
Ethernet parameter editor.
Parameter 40GbE Value
40GBASE-KR4 Value
100GbE Value 40GbE at 24.24 Gbps 100GbE at CAUI–4
Lanes
4 10 4 4
Data rate per lane
10312.5 Mbps 10312.5 Mbps 6250.0 Mbps 25781.25 Mbps
Available PHY
reference clock
frequencies
644.53125 MHz
322.265625 MHz
644.53125 MHz
322.265625 MHz
390.625 MHz
195.3125 MHz
644.53125 MHz
Related Information
• Clocks on page 3-51
The range and default settings for the PHY reference frequency parameter depend on the PHY
configuration parameter value. The PHY reference frequency value is the required frequency of the
transceiver reference clock or transceiver reference clocks.
UG-01088
2014.12.15
IP Core Parameters
2-9
Getting Started
Altera Corporation
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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