Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Bedienungsanleitung Seite 27
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Parameter Type Range Default Setting Parameter Description
PHY reference
frequency
(2)
Integer
(encodi
ng)
The range and default settings depend
on the PHY configuration.
Despite its apparent availability in the
parameter editor, CAUI–4 variations
do not support the 322.265625 MHz
clock frequency. For correct
functioning of CAUI–4 variations, you
must set this parameter to the value of
644.53125 MHz.
Sets the expected incoming PHY
clk_ref reference frequency. The
input clock frequency must match
the frequency you specify for this
parameter.
In Sync-E variations, the input clock
frequencies for the rx_ref_clk and
tx_ref_clk clocks must match the
frequency you specify for this
parameter, although the two clocks
can be driven from different sources
and need not be aligned with each
other.
Advanced Design Options
Status clock
rate
(2)
Float • Stratix IV:
37.5–50.0
• Arria V GZ or
Stratix V:
100.0–125.0
• Stratix IV: 37.5
• Arria V GZ or
Stratix V: 100.0
Sets the clock rate of clk_status in
MHz.
Statistics
counters
(5)
Boolean • True
• False
True If turned on, the IP core includes
built–in statistics counters. If turned
off, the IP core is configured without
statistics counters.
Enable SyncE
support
Boolean • True
• False
False Enables or disables a separate
reference clock for the RX CDR
block in the transceiver and exposes
the RX recovered clock as an output
signal. If this option is turned on
(set to true), the TX PLL and the RX
CDR in the transceiver have
separate input reference clocks and
the RX recovered clock is visible as
an IP core output signal. If it is
turned off, the two PLLs share one
input reference clock and the RX
recovered clock is not available as an
output signal.
UG-01088
2014.12.15
IP Core Parameters
2-5
Getting Started
Altera Corporation
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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