Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Bedienungsanleitung Seite 118
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The following 40-100GbE MAC and PHY IP core signals are not available in MAC-only IP core
variations:
• Clock signals:
• clk_ref (relevant only for IP core variations with the Sync–E support option turned off)
• tx_clk_ref (relevant only for IP core variations with the Sync-E support option turned on)
• rx_clk_ref (relevant only for IP core variations with the Sync-E support option turned on)
• rx_recovered_clk (relevant only for IP core variations with the Sync-E support option turned on)
• PCS and PMA reset signals:
• pcs_tx_arst_ST
• pcs_rx_arst_ST
• pma_arst_ST
• Ethernet link signals tx_serial and rx_serial
• PHY output status signals tx_lanes_stable and lanes_deskewed. Note that input signals with these
names are available, and should be supplied by the user logic that implements the PHY layer.
• Signals to connect to the external transceiver reconfiguration controller (relevant for Arria V GZ and
Stratix V devices only).
• 40GBASE-KR4 microprocessor interface and reconfiguration interface signals.
Table 3-21: 40-100GbE MAC IP Core Signals Not Visible in 40-100GbE MAC and PHY IP Core
Signal Name Direction Description
Transmit Side Signals
tx_mii_d[<w>*64-1:0]
Output
MAC to PHY connection
interface
tx_mii_c[<w>*8-1:0]
Output
tx_mii_valid
Output
tx_mii_ready
Input
tx_lanes_stable
Input
Receive Side Signals
rx_mii_d[<w>*64-1:0]
Input
PHY to MAC connection
interface
rx_mii_c[<w>*8-1:0]
Input
rx_mii_valid
Input
lanes_deskewed
Input Lane to lane deskew interface
Note: When simulating the full design the lanes_deskewed input comes from the output of the RX PCS,
indicating a fully locked status. To avoid confusion, when simulating the alt_e40_mac or
alt_e100_mac wrapper as the top level, drive the lanes_deskewed input and the tx_mii_ready
input to '1'.
UG-01088
2014.12.15
Signals of 40-100GbE MAC‑Only IP Core Variations
3-71
Functional Description
Altera Corporation
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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