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June 2012 1.0 • Updated for use with version 12.0 of the Quartus II software.
• Updated address map.
• Updated device family support.
• Updated interfaces for 40-100GbE IP cores with adapters and without
adapters. Additional interfaces include:
• MAC and PHY asynchronous resets.
• MAC to PHY connections.
• Lane-to-lane deskew.
• Statistics counters increment vectors.
• Link fault signaling, including remote fault and local fault.
• Updated RTL hierarchy, directory structure, and wrapper reorganiza‐
tion.
• Feature additions:
• Controllable FCS (CRC) insertion and removal.
• Cut-through mode runt removal.
• PCS BER monitor.
• PCS test pattern generation and check.
• Reduced RX destination MAC address checking from 16 addresses to
1 address.
• Preserved FCS result.
• Statistics counters implemented as a synthesis option.
• Updated or added software registers:
• Test pattern counter.
• Link fault signaling.
• CRC configuration.
• MAC hardware error.
• MAC and PHY resets.
• PCS hardware error.
• BER monitor.
• Test mode.
• MAC address.
• Statistics counters: roll-overs and increment vectors.
• Clocking revisions:
• clk50 has been removed and replaced by clk_status.
• clk_din/clk_txmac and clk_dout/clk_rxmac have been added as
TX and RX input clocks.
• Additional parameters: STATS_CNTRS_OPTION and FAST_SIMULATION.
• Updated testbenches and simulation examples.
• Updated reset signals and reset bits.
• Additional information regarding oversized frames.
UG-01088
2014.12.15
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision
History
D-7
Additional Information
Altera Corporation
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- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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