Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Bedienungsanleitung Seite 155
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Address Name Bit Description HW Reset
Value
Access
0x160 DST_AD0_LO [23:0] Destination address 0 (lower 24 bits). 0x00000000 RW
0x161 DST_AD0_HI [23:0] Destination address 0 (upper 24 bits). 0x00000000 RW
0x162-
0x17f
RESERVED
[31:0] Reserved. 0x0000000
0
The MADDR_CTRL register bits 0 and 30 together with the RX_FILTER_CTRL register bit 0 (offset 0x103,
Table 3–37 on page 3–59) control address checking as follows:
Table 3-47: Destination Address Checking Behavior
RX_FILTER_CTRL[0] MADDR_
CTRL[30]
MADDR_
CTRL[0]
Behavior
1 — — Promiscuous receive mode: IP core accepts frames
regardless of destination address.
0
0 — IP core treats all packets as if they have a matching
address. (However, the IP core may filter packets
based on other criteria).
1 0 IP core treats all packets as if they have a destination
address that does not match (and therefore, accepts
no packets).
1 1 IP core performs destination address checking and
filters out packets whose destination address does
not match the address specified in the DST_AD0_LO
and DST_AD0_HI registers.
Related Information
Address Checking on page 3-24
Describes the register setting requirements to specify address checking.
Statistics Registers
The statistics registers count Ethernet traffic and errors. The 64-bit statistics registers are designed to roll
over, to ensure timing closure on the FPGA. However, these registers should never roll over if the link is
functioning properly. The statistics registers check the size of frames, which includes the following fields:
• Size of the destination address
• Size of the source address
• Size of the data
• Four bytes of CRC
The statistics counters module is a synthesis option. The statistics registers are counters that are
implemented inside the CSR. When you turn on the Statistics counters parameter in the 40-100GbE
parameter editor, the counters are implemented in the CSR. When you turn off the Statistics counters
3-108
Statistics Registers
UG-01088
2014.12.15
Altera Corporation
Functional Description
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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