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December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide
1. Introduction
The Altera
®
Transceiver PHY IP Core User Guide describes the following
protocol-specific PHYs:
■ 10GBASE-R PHY IP Core
■ XAUI PHY IP Core
■ Interlaken PHY IP Core
■ PCI Express PHY (PIPE) IP Core
■ Custom PHY IP Core
■ Low Latency PHY IP Core
The protocol-specific PHYs automatically configure settings for the physical coding
sublayer (PCS) module, leaving a small number of parameters in the physical media
attachment (PMA) module for you to configure. You can use the Custom PHY for
applications that require more flexible settings. The design of all of these PHYs is
modular and uses standard interfaces. All PHYs include an Avalon
®
Memory-Mapped (Avalon-MM) interface to access control and status registers and an
Avalon Streaming (Avalon-ST) interface to connect to the MAC for data transfer. The
control and status registers store device-dependent information about the PCS and
PMA modules. You can access this device-dependent information using the
device-independent Avalon-MM interface, reducing overall complexity of your
design and the number of device-dependent signals that you must expose in your
top-level module.
f For more information about the Avalon-MM and Avalon-ST protocols, including
timing diagrams, refer to the Avalon Interface Specifications.
Table 1–1 shows hard and soft implementation support for these IP cores in Stratix
®
V
devices. Typically, the PCS and PMA are implemented as hard logic, saving FPGA
resources and reducing the complexity of verification. In some cases, the PCS is also
available in soft logic as Table 1–1 indicates.
Table 1–1. Stratix V GX Support for Protocol Specific PHY IP Cores
PHY Protocol Soft PCS Hard PCS Hard PMA
10GBASE-R No Yes Yes
XAUI Yes No Yes
Interlaken No Yes Yes
PCI Express Gen1 and Gen2 No Yes Yes
Custom PHY No Yes Yes
Low latency PHY No Yes Yes
- User Guide 1
- Contents 3
- Chapter 7. Custom PHY IP Core 4
- 1. Introduction 7
- PHY - Stratix V 8
- Reset Controller 9
- Transceiver 10
- Channel PLL 10
- Figure 1–4 12
- Note to Table 1–2: 12
- Transceiver PHY 13
- Avalon-MM PHY Management 14
- Serial Loopback 14
- Unsupported Features 14
- 2. Getting Started 15
- Specifying Parameters 16
- Simulate the IP Core 18
- 3. 10GBASE-R PHY IP Core 19
- Stratix V FPGA 20
- Release Information 21
- Device Family Support 21
- Parameter Settings 22
- Interfaces 23
- SDR XGMII TX Interface 24
- SDR XGMII RX Interface 25
- Avalon-MM Interface 26
- Status Interface 29
- Clocks, Reset, and Powerdown 29
- Table 3–12. Clock Signals 31
- TimeQuest Timing Constraints 32
- 4. XAUI PHY IP Core 35
- Configurations 38
- PMA Channel Controller 48
- (Optional) 48
- ■ 1–enables serial loopback 49
- ■ 0–disables serial loopback 49
- 5. Interlaken PHY IP Core 53
- Interface 55
- Avalon-ST TX Interface 56
- Avalon-ST RX Interface 57
- PLL Interface 60
- TX and RX Serial Interface 60
- Optional Clocks for Deskew 61
- ■ The simulation language 62
- ■ The name of your testbench 62
- Simulation Testbench 63
- Resource Utilization 66
- PCI Express PIPE 69
- Hard PCS and PMA 69
- PHY Management Signals 70
- PIPE Interface 73
- ■ 1'b0: -6 dB 73
- ■ 1'b1: -3.5 dB 73
- Note to Table 6–8: 74
- Transceiver Serial Interface 75
- Simulation 76
- 7. Custom PHY IP Core 79
- General Options 80
- 8B/10B Encoder and Decoder 82
- Word Alignment 83
- Rate Match FIFO 84
- Byte Ordering 85
- Custom PHY PCS and PMA 88
- Custom PHY IP Core 88
- Clock Interface 91
- Optional Status Signals 92
- Note to Table 7–14: 93
- 8. Low Latency PHY IP Core 95
- Note to Table 8–3: 98
- ■ 0–0 dB 99
- ■ 1–3 dB 99
- ■ 2–6 dB 99
- ■ 3–9 dB 99
- ■ 4–12 dB 99
- PMA and Light-Weight PCS 100
- Register Descriptions 101
- Serial Data Interface 102
- Optional Status Interface 102
- Controller 103
- Parameter Differences 107
- Port Differences 108
- XAUI PHY 109
- PCI Express PHY (PIPE) 112
- Note to Table 10–4: 113
- Custom PHY 116
- Additional Information 117
- Info–2 Additional Information 118
- Revision History 118
- ■ Initial release 119
- Info–4 Additional Information 120
- Typographic Conventions 120
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