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1–6 Chapter 1: Introduction
Reset Controller
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
The reset controller also includes a signal to power down the PLLs and transceiver
channels:
■
pll_powerdown
—This signal powers down a single clock generation circuit.
pll_powerdown
is only asserted during a full reset sequence, which is only possible
when the device enters user mode or when you assert and deassert the PHY
management interface reset input.
1 The Quartus
®
II software automatically selects the power-down channel feature,
which takes effect when you configure the Stratix IV or Stratix V device. All unused
channels and blocks consume no power, reducing overall power consumption.
Table 1–2 lists the bonding requirements for the protocol-specific PHYs.
The precise sequence of events that occurs to reset the transceiver PHY depends upon
the configuration chosen. The reset sequence for configurations that only include TX
channels is far simpler because it does not require the RX analog logic to recover the
clock from the input data stream or to perform offset cancellation. Figure 1–4
illustrates the critical signals of the reset circuitry for a duplex PHY. As this figure
illustrates, the typical reset sequence includes the following steps:
1. After the PLL locks,
tx_ready
is asserted.
2. After offset cancellation completes
rx_oc_busy
is deasserted. (Offset cancellation
corrects for process variations which may result in analog voltages that are offset
from the required ranges.)
Table 1–2. Bonding Requirements
Protocol Bonded Non-Bonded
10GBASE-R — v
XAUI v —
Interlaken < ×4 — v
Interlaken > ×4 v —
PCI Express ×1 — v
PCI Express ×2, ×4, ×8 v —
Custom PHY (1) vv
Low Latency PHY (1) vv
Note to Table 1–2:
(1) You can choose either bonded or non-bonded clocks for the Custom and Low Latency PHY IP cores to meet the
requirements of your design.
- User Guide 1
- Contents 3
- Chapter 7. Custom PHY IP Core 4
- 1. Introduction 7
- PHY - Stratix V 8
- Reset Controller 9
- Transceiver 10
- Channel PLL 10
- Figure 1–4 12
- Note to Table 1–2: 12
- Transceiver PHY 13
- Avalon-MM PHY Management 14
- Serial Loopback 14
- Unsupported Features 14
- 2. Getting Started 15
- Specifying Parameters 16
- Simulate the IP Core 18
- 3. 10GBASE-R PHY IP Core 19
- Stratix V FPGA 20
- Release Information 21
- Device Family Support 21
- Parameter Settings 22
- Interfaces 23
- SDR XGMII TX Interface 24
- SDR XGMII RX Interface 25
- Avalon-MM Interface 26
- Status Interface 29
- Clocks, Reset, and Powerdown 29
- Table 3–12. Clock Signals 31
- TimeQuest Timing Constraints 32
- 4. XAUI PHY IP Core 35
- Configurations 38
- PMA Channel Controller 48
- (Optional) 48
- ■ 1–enables serial loopback 49
- ■ 0–disables serial loopback 49
- 5. Interlaken PHY IP Core 53
- Interface 55
- Avalon-ST TX Interface 56
- Avalon-ST RX Interface 57
- PLL Interface 60
- TX and RX Serial Interface 60
- Optional Clocks for Deskew 61
- ■ The simulation language 62
- ■ The name of your testbench 62
- Simulation Testbench 63
- Resource Utilization 66
- PCI Express PIPE 69
- Hard PCS and PMA 69
- PHY Management Signals 70
- PIPE Interface 73
- ■ 1'b0: -6 dB 73
- ■ 1'b1: -3.5 dB 73
- Note to Table 6–8: 74
- Transceiver Serial Interface 75
- Simulation 76
- 7. Custom PHY IP Core 79
- General Options 80
- 8B/10B Encoder and Decoder 82
- Word Alignment 83
- Rate Match FIFO 84
- Byte Ordering 85
- Custom PHY PCS and PMA 88
- Custom PHY IP Core 88
- Clock Interface 91
- Optional Status Signals 92
- Note to Table 7–14: 93
- 8. Low Latency PHY IP Core 95
- Note to Table 8–3: 98
- ■ 0–0 dB 99
- ■ 1–3 dB 99
- ■ 2–6 dB 99
- ■ 3–9 dB 99
- ■ 4–12 dB 99
- PMA and Light-Weight PCS 100
- Register Descriptions 101
- Serial Data Interface 102
- Optional Status Interface 102
- Controller 103
- Parameter Differences 107
- Port Differences 108
- XAUI PHY 109
- PCI Express PHY (PIPE) 112
- Note to Table 10–4: 113
- Custom PHY 116
- Additional Information 117
- Info–2 Additional Information 118
- Revision History 118
- ■ Initial release 119
- Info–4 Additional Information 120
- Typographic Conventions 120
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