Altera UG-01080 Betriebsanweisung PDF herunterladen (Seite 11)

Chapter 1: Introduction 1–5

Reset Controller

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide

In non-bonded mode, separate CGBs are used for each channel and the skew between

channels is not carefully controlled. Figure 1–3 illustrates mode for Stratix V devices.

The reset controller generates a reset sequence appropriate for the protocol. Using the

reset controller section of the memory map, you can choose have the reset sequence

apply to all channels (the default behavior), or mask out some channels so that those

channels will not be affected by the reset sequence. For bonded modes, you should

allow the reset sequence to affect all channels.

The reset controller drives the following reset signals:

■

rx_analogreset

—This signal resets the analog CDR and deserializer logic present

in the RX channel. (CDR is the first step of the power-up process.)

■

rx_digitalreset

—This signal resets all digital logic in the RX PCS and PMA.

■

tx_digitalreset

—This signal resets all logic in the TX PCS.

Figure 1–3. Stratix V Device Non-Bonded Mode Clocking

Transceiver

PMA PCS

Reference

clock input

High

frequency

clock

Low speed

parallel

clock(s)

FPGA-fabric

interface

Data

Clock

Tx PLL

Clock Gen

Buffer

(CGB)

/n, /m

Ser

Ser = Serializer

DeSer = DeSerializer

CDR

Tx PCS

Rx PCS

PMA PCS

Tx data

Rx data

DeSer

Transceiver

PMA PCS

Low speed

parallel

clock(s)

Clock Gen

Buffer

(CGB)

/n, /m

Ser

CDR

Tx PCS

Rx PCS

PMA PCS

Rx data

DeSer

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 119 120

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