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Info–2 Additional Information
Revision History
Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation
Interlaken PHY Transceiver
December
2010
1.1
■ Added simulation support in ModelSim SE, Synopsys VCS MX, Cadence NCSim
■ Changed number of lanes supported from 4–24 to 1–24.
■ Changed reference clock to be 1/20th rather than 1/10th the lane rate.
■ Renamed management interface, adding
phy_
prefix
■ Changed
phy_mgmt_address
from 16 to 9 bits.
■ Changed many signal names, refer to Figure 5–2 on page 5–4.Changed register map to
show word addresses instead of a byte offset from a base address.
PCI Express PHY (PIPE)
December
2010
1.1
■ Added simulation support in ModelSim SE
■ Added PIPE low latency configuration option
■ Changed
phy_mgmt_address
from 16 to 9 bits.
■ Changed register map to show word addresses instead of a byte offset from a base address.
■ Added
tx_ready
,
rx_ready
,
pipe_txswing
, and
pipe_rxeleciidle
signals
■ Added
rx_errdetect
,
rx_disperr
, and
rx_a1a2sizeout
register fields
Custom PHY Transceiver
December
2010
1.1
■ Added support for 8B/10B encoding and decoding in Stratix V devices
■ Added support for rate matching in Stratix V devices.
■ Added support for Arria II GX, Arria II GZ, HardCopy IV GX, and Stratix IV GX devices
■ Renamed management interface, adding
phy_
prefix
■ Changed
phy_mgmt_address
from 8 to 9 bits.
■ Added many optional status ports and renamed some signals. Refer to Figure 7–4 on
page 7–8 and subsequent signal descriptions.
■ Changed register map to show word addresses instead of a byte offset from a base address.
Low Latency PHY IP Core
December
2010
1.1
■ Renamed management interface, adding
phy_
prefix
■ Changed
phy_mgmt_address
from 16 to 9 bits.
■ Changed register map to show word addresses instead of a byte offset from a base address.
■ Removed
rx_offset_cancellation_done
signal. Internal reset logic determines when
offset cancellation has completed.
■ Removed support for Stratix IV GX devices.
Transceiver Reconfiguration Controller
December
2010
1.1
■ Reconfiguration is now integrated into the XAUI PHY IP core and 10GBASE-R PHY IP core.
■ Revised register map to show word addresses instead of a byte offset from a base address.
Migrating from Stratix IV to Stratix V
December
2010
1.1
■ Changed
phy_mgmt_address
from 16 to 9 bits.
Date Version Changes Made SPR
- User Guide 1
- Contents 3
- Chapter 7. Custom PHY IP Core 4
- 1. Introduction 7
- PHY - Stratix V 8
- Reset Controller 9
- Transceiver 10
- Channel PLL 10
- Figure 1–4 12
- Note to Table 1–2: 12
- Transceiver PHY 13
- Avalon-MM PHY Management 14
- Serial Loopback 14
- Unsupported Features 14
- 2. Getting Started 15
- Specifying Parameters 16
- Simulate the IP Core 18
- 3. 10GBASE-R PHY IP Core 19
- Stratix V FPGA 20
- Release Information 21
- Device Family Support 21
- Parameter Settings 22
- Interfaces 23
- SDR XGMII TX Interface 24
- SDR XGMII RX Interface 25
- Avalon-MM Interface 26
- Status Interface 29
- Clocks, Reset, and Powerdown 29
- Table 3–12. Clock Signals 31
- TimeQuest Timing Constraints 32
- 4. XAUI PHY IP Core 35
- Configurations 38
- PMA Channel Controller 48
- (Optional) 48
- ■ 1–enables serial loopback 49
- ■ 0–disables serial loopback 49
- 5. Interlaken PHY IP Core 53
- Interface 55
- Avalon-ST TX Interface 56
- Avalon-ST RX Interface 57
- PLL Interface 60
- TX and RX Serial Interface 60
- Optional Clocks for Deskew 61
- ■ The simulation language 62
- ■ The name of your testbench 62
- Simulation Testbench 63
- Resource Utilization 66
- PCI Express PIPE 69
- Hard PCS and PMA 69
- PHY Management Signals 70
- PIPE Interface 73
- ■ 1'b0: -6 dB 73
- ■ 1'b1: -3.5 dB 73
- Note to Table 6–8: 74
- Transceiver Serial Interface 75
- Simulation 76
- 7. Custom PHY IP Core 79
- General Options 80
- 8B/10B Encoder and Decoder 82
- Word Alignment 83
- Rate Match FIFO 84
- Byte Ordering 85
- Custom PHY PCS and PMA 88
- Custom PHY IP Core 88
- Clock Interface 91
- Optional Status Signals 92
- Note to Table 7–14: 93
- 8. Low Latency PHY IP Core 95
- Note to Table 8–3: 98
- ■ 0–0 dB 99
- ■ 1–3 dB 99
- ■ 2–6 dB 99
- ■ 3–9 dB 99
- ■ 4–12 dB 99
- PMA and Light-Weight PCS 100
- Register Descriptions 101
- Serial Data Interface 102
- Optional Status Interface 102
- Controller 103
- Parameter Differences 107
- Port Differences 108
- XAUI PHY 109
- PCI Express PHY (PIPE) 112
- Note to Table 10–4: 113
- Custom PHY 116
- Additional Information 117
- Info–2 Additional Information 118
- Revision History 118
- ■ Initial release 119
- Info–4 Additional Information 120
- Typographic Conventions 120
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