Altera Stratix V Avalon-ST Bedienungsanleitung Seite 72
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Signal Direction Description
powerdown0[1:0] Output Power down <n>. This signal requests the PHY to change its
power state to the specified state (P0, P0s, P1, or P2).
rxdata0[31:0] Input Receive data. This bus receives data on lane <n>.
rxdatak0[3:0]
Input Data/Control bits for the symbols of receive data. Bit 0
corresponds to the lowest-order byte of rxdata, and so on. A
value of 0 indicates a data byte. A value of 1 indicates a control
byte. For Gen1 and Gen2 only.
rxelecidle0 Input Receive electrical idle <n>. When asserted, indicates detection of
an electrical idle.
rxpolarity0 Output Receive polarity <n>. This signal instructs the PHY layer to
invert the polarity of the 8B/10B receiver decoding block.
rxstatus0[2:0] Input Receive status <n>. This signal encodes receive status and error
codes for the receive data stream and receiver detection.
rxvalid0 Input Receive valid <n>. This symbol indicates symbol lock and valid
data on rxdata<n> and rxdatak <n>.
sim_pipe_
ltssmstate0[4:0]
Input and
Output
LTSSM state: The LTSSM state machine encoding defines the
following states:
• 5’b00000: Detect.Quiet
• 5’b 00001: Detect.Active
• 5’b00010: Polling.Active
• 5’b 00011: Polling.Compliance
• 5’b 00100: Polling.Configuration
• 5’b00101: Polling.Speed
• 5’b00110: config.LinkwidthsStart
• 5’b 00111: Config.Linkaccept
• 5’b 01000: Config.Lanenumaccept
• 5’b01001: Config.Lanenumwait
• 5’b01010: Config.Complete
• 5’b 01011: Config.Idle
• 5’b01100: Recovery.Rcvlock
• 5’b01101: Recovery.Rcvconfig
• 5’b01110: Recovery.Idle
• 5’b 01111: L0
• 5’b10000: Disable
• 5’b10001: Loopback.Entry
• 5’b10010: Loopback.Active
UG-01097_sriov
2014.12.15
PIPE Interface Signals
4-37
Interfaces and Signal Descriptions
Altera Corporation
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- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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