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Signal Direction Description
tx_st_valid
(3)
Input Clocks tx_st_data to the core when tx_st_ready is also
asserted. Between tx_st_sop and tx_st_eop, tx_st_valid must
not be deasserted in the middle of a TLP except in response to
tx_st_ready deassertion. When tx_st_ready deasserts, this
signal must deassert within 1 or 2 clock cycles. When tx_st_
ready reasserts, and tx_st_data is in mid-TLP, this signal must
reassert within 2 cycles. The figure entitled 64-Bit Transaction
Layer Backpressures the Application Layer illustrates the timing of
this signal.
To facilitate timing closure, Altera recommends that you register
both the tx_st_ready and tx_st_valid signals. If no other
delays are added to the ready-valid latency, the resulting delay
corresponds to a readyLatency of 2.
tx_st_empty[1:0]
Input Indicates the number of qwords that are empty during cycles that
contain the end of a packet. When asserted, the empty dwords
are in the high-order bits. Valid only when tx_st_eop is asserted.
Not used when tx_st_data is 64 bits. For 128-bit data, only bit 0
applies and indicates whether the upper qword contains data. For
256-bit data, both bits are used to indicate the number of upper
words that contain data, resulting in the following encodings for
the 128-and 256-bit interfaces:
128-Bit interface: tx_st_empty = 0, tx_st_data[127:0]contains
valid data tx_st_empty = 1, tx_st_data[63:0] contains valid
data.
256-bit interface:tx_st_empty = 0, tx_st_data[255:0] contains
valid datatx_ st_empty = 1, tx_st_data[191:0] contains valid
data tx_st_empty = 2, tx_st_data[127:0] contains valid data
tx_st_empty = 3, tx_st_data[63:0] contains valid data.
tx_st_err
Input Indicates an error on transmitted TLP. This signal is used to
nullify a packet. It should only be applied to posted and
completion TLPs with payload. To nullify a packet, assert this
signal for 1 cycle after the SOP and before the EOP. When a
packet is nullified, the following packet should not be transmitted
until the next clock cycle. tx_st_err is not available for packets
that are 1 or 2 cycles long.
Refer to the figure entitled 128-Bit Avalon-ST tx_st_data Cycle
Definition for 3-Dword Header TLP with non-Qword Aligned
Address for a timing diagram that illustrates the use of the error
signal. Note that it must be asserted while the valid signal is
asserted.
UG-01097_sriov
2014.12.15
Avalon-ST TX Interface
4-3
Interfaces and Signal Descriptions
Altera Corporation
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- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
Verwandte Produkte und Handbücher für Messgeräte Altera Stratix V Avalon-ST
Messgeräte Altera SDI HSMC Bedienungsanleitung
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