Altera Integer Arithmetic IP Bedienungsanleitung PDF herunterladen (Seite 63)

The following figure shows the double accumulator implementation.

Figure 6-12: Double Accumulator

Mult0

Mult1

Accumulator feedba ck

Output result

+/-

Double Accu mulator Register

Output Register

Verilog HDL Prototype

The following Verilog HDL prototype is located in the Verilog Design File (.v) in the <Quartus II installa‐

tion directory>\eda\synthesis directory.

VHDL Component Declaration

The VHDL component declaration is located in the VHDL Design File (.vhd) in the <Quartus II installa‐

tion directory> directory.

VHDL LIBRARY_USE Declaration

The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component Declaration.

LIBRARY altera_mf;

USE altera_mf.altera_mf_components.all;

Ports

The following tables list the input and output ports of the ALTERA_MULT_ADD megafunction.

Table 6-1: ALTERA_MULT_ADD MegaFunction Input Ports

Port name Required Description

dataa [] Yes Data input to the multiplier. Input port [NUMBER_OF_

MULTIPLIERS * WIDTH_A - 1 … 0] wide

6-10

Verilog HDL Prototype

UG-01063

2014.12.19

Altera Corporation

ALTERA_MULT_ADD (Multiply-Adder)

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Altera Integer Arithmetic IP Bedienungsanleitung Seite 63