Altera Integer Arithmetic IP Bedienungsanleitung Seite 3
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ALTECC (Error Correction Code: Encoder/Decoder).......................................5-1
ALTECC_ENCODER Features..................................................................................................................5-2
Resource Utilization and Performance.....................................................................................................5-3
Verilog HDL Prototype (ALTECC_ENCODER)....................................................................................5-5
Verilog HDL Prototype (ALTECC_DECODER)....................................................................................5-5
VHDL Component Declaration (ALTECC_ENCODER)..................................................................... 5-6
VHDL Component Declaration (ALTECC_DECODER)..................................................................... 5-6
VHDL LIBRARY_USE Declaration..........................................................................................................5-7
Ports (ALTECC_ENCODER)....................................................................................................................5-7
Ports (ALTECC_DECODER)....................................................................................................................5-7
Parameters (ALTECC_ENCODER)..........................................................................................................5-8
Parameters (ALTECC_DECODER)..........................................................................................................5-8
Design Example 1: ALTECC_ENCODER................................................................................................5-9
Understanding the Simulation Results......................................................................................... 5-9
Design Example 2: ALTECC_DECODER..............................................................................................5-12
Understanding the Simulation Results.......................................................................................5-12
ALTERA_MULT_ADD (Multiply-Adder)......................................................... 6-1
Features......................................................................................................................................................... 6-2
Pre-adder...........................................................................................................................................6-3
Systolic Delay Register.....................................................................................................................6-6
Pre-load Constant............................................................................................................................6-9
Double Accumulator.......................................................................................................................6-9
Verilog HDL Prototype.............................................................................................................................6-10
VHDL Component Declaration.............................................................................................................. 6-10
VHDL LIBRARY_USE Declaration........................................................................................................6-10
Ports.............................................................................................................................................................6-10
ALTERA_MULT_ADD Parameters.......................................................................................................6-12
Design Example: Implementing a Simple Finite Impulse Response (FIR) Filter.............................6-19
Understanding the Simulation Results...................................................................................................6-20
ALTMEMMULT (Memory-based Constant Coefficient Multiplier).................7-1
Features......................................................................................................................................................... 7-1
Resource Utilization and Performance.....................................................................................................7-2
Verilog HDL Prototype...............................................................................................................................7-2
VHDL Component Declaration................................................................................................................ 7-3
Ports...............................................................................................................................................................7-3
Parameters.....................................................................................................................................................7-4
Design Example: 8 × 8 Multiplier..............................................................................................................7-5
Understanding the Simulation Results..................................................................................................... 7-6
ALTMULT_ACCUM (Multiply-Accumulate)....................................................8-1
Features......................................................................................................................................................... 8-2
Resource Utilization and Performance.....................................................................................................8-2
Integer Arithmetic IP Cores User Guide
TOC-3
Altera Corporation
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- IP Cores Function Overview 6
- Design Example Files 7
- Using the Parameter Editor 9
- UG-01063 10
- 2014.12.19 10
- Legacy parameter 12
- Upgrading IP Cores 13
- Related Information 16
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Simulating Altera Designs 18
- LPM_COUNTER (Counter) 19
- LPM_DIVIDE (Divider) 26
- LPM_MULT (Multiplier) 32
- LPM_MULT Ports 34
- LPM_MULT Parameters 35
- Decoder) 39
- ALTECC_ENCODER Features 40
- Ports (ALTECC_ENCODER) 45
- Ports (ALTECC_DECODER) 45
- Parameters (ALTECC_ENCODER) 46
- Parameters (ALTECC_DECODER) 46
- ALTERA_MULT_ADD 54
- ALTERA_MULT_ADD Parameters 65
- Coefficient Multiplier) 74
- ALTMULT_ACCUM 82
- ALTMULT_ACCUM Ports 85
- ALTMULT_ACCUM Parameters 87
- Altera Corporation 101
- Send Feedback 101
- ALTMULT_ADD (Multiply-Adder) 102
- ALTMULT_ADD 103
- Features 104
- Pre-adder 105
- Pre-adder Input Mode 106
- Pre-adder Square Mode 106
- Pre-adder Constant Mode 107
- Systolic Delay Register 108
- Pre-load Constant 111
- Double Accumulator 111
- Verilog HDL Prototype 112
- VHDL Component Declaration 112
- VHDL LIBRARY_USE Declaration 113
- ALTMULT_ADD Ports 113
- ALTMULT_ADD Parameters 115
- Parameter Name Type Requi 116
- Description 116
- Subscribe 138
- Complex Multiplication 139
- Canonical Representation 139
- Conventional Representation 140
- ALTMULT_COMPLEX Ports 143
- ALTMULT_COMPLEX Parameters 143
- ALTSQRT (Integer Square Root) 147
- Parameters 149
- PARALLEL_ADD (Parallel Adder) 151
- Document Revision History 156
- Date Version Changes 157
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