Altera Integer Arithmetic IP Bedienungsanleitung Seite 4
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Verilog HDL Prototype...............................................................................................................................8-4
VHDL Component Declaration................................................................................................................ 8-4
VHDL LIBRARY_USE Declaration..........................................................................................................8-4
ALTMULT_ACCUM Ports........................................................................................................................8-4
ALTMULT_ACCUM Parameters.............................................................................................................8-6
Design Example: Shift Accumulator.......................................................................................................8-19
Understanding the Simulation Results...................................................................................................8-19
ALTMULT_ADD (Multiply-Adder)...................................................................9-1
Features......................................................................................................................................................... 9-3
Pre-adder...........................................................................................................................................9-4
Systolic Delay Register.....................................................................................................................9-7
Pre-load Constant..........................................................................................................................9-10
Double Accumulator.....................................................................................................................9-10
Resource Utilization and Performance...................................................................................................9-11
Verilog HDL Prototype.............................................................................................................................9-11
VHDL Component Declaration.............................................................................................................. 9-11
VHDL LIBRARY_USE Declaration........................................................................................................9-12
ALTMULT_ADD Ports............................................................................................................................9-12
ALTMULT_ADD Parameters................................................................................................................. 9-14
Design Example: Implementing a Simple Finite Impulse Response (FIR) Filter.............................9-34
Understanding the Simulation Results...................................................................................................9-35
ALTMULT_COMPLEX (Complex Multiplier)................................................ 10-1
Complex Multiplication............................................................................................................................10-2
Canonical Representation.........................................................................................................................10-2
Conventional Representation...................................................................................................................10-3
Features....................................................................................................................................................... 10-3
Resource Utilization and Performance...................................................................................................10-4
Verilog HDL Prototype.............................................................................................................................10-4
VHDL Component Declaration.............................................................................................................. 10-5
VHDL LIBRARY_USE Declaration........................................................................................................10-5
ALTMULT_COMPLEX Ports.................................................................................................................10-6
ALTMULT_COMPLEX Parameters.......................................................................................................10-6
Design Example: Multiplication of 8-bit Complex Numbers Using Canonical Representation...
10-8
Understanding the Simulation Results...................................................................................................10-8
ALTSQRT (Integer Square Root)..................................................................... 11-1
Features....................................................................................................................................................... 11-1
Resource Utilization and Performance...................................................................................................11-1
Verilog HDL Prototype.............................................................................................................................11-2
VHDL Component Declaration.............................................................................................................. 11-2
VHDL LIBRARY_USE Declaration........................................................................................................11-3
Ports.............................................................................................................................................................11-3
Parameters.................................................................................................................................................. 11-3
TOC-4
Integer Arithmetic IP Cores User Guide
Altera Corporation
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- IP Cores Function Overview 6
- Design Example Files 7
- Using the Parameter Editor 9
- UG-01063 10
- 2014.12.19 10
- Legacy parameter 12
- Upgrading IP Cores 13
- Related Information 16
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Simulating Altera Designs 18
- LPM_COUNTER (Counter) 19
- LPM_DIVIDE (Divider) 26
- LPM_MULT (Multiplier) 32
- LPM_MULT Ports 34
- LPM_MULT Parameters 35
- Decoder) 39
- ALTECC_ENCODER Features 40
- Ports (ALTECC_ENCODER) 45
- Ports (ALTECC_DECODER) 45
- Parameters (ALTECC_ENCODER) 46
- Parameters (ALTECC_DECODER) 46
- ALTERA_MULT_ADD 54
- ALTERA_MULT_ADD Parameters 65
- Coefficient Multiplier) 74
- ALTMULT_ACCUM 82
- ALTMULT_ACCUM Ports 85
- ALTMULT_ACCUM Parameters 87
- Altera Corporation 101
- Send Feedback 101
- ALTMULT_ADD (Multiply-Adder) 102
- ALTMULT_ADD 103
- Features 104
- Pre-adder 105
- Pre-adder Input Mode 106
- Pre-adder Square Mode 106
- Pre-adder Constant Mode 107
- Systolic Delay Register 108
- Pre-load Constant 111
- Double Accumulator 111
- Verilog HDL Prototype 112
- VHDL Component Declaration 112
- VHDL LIBRARY_USE Declaration 113
- ALTMULT_ADD Ports 113
- ALTMULT_ADD Parameters 115
- Parameter Name Type Requi 116
- Description 116
- Subscribe 138
- Complex Multiplication 139
- Canonical Representation 139
- Conventional Representation 140
- ALTMULT_COMPLEX Ports 143
- ALTMULT_COMPLEX Parameters 143
- ALTSQRT (Integer Square Root) 147
- Parameters 149
- PARALLEL_ADD (Parallel Adder) 151
- Document Revision History 156
- Date Version Changes 157
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