Altera Cyclone V GX FPGA Development Board Bedienungsanleitung PDF herunterladen (Seite 49)

Chapter 2: Board Components 2–41

Memory

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

DDR3B_A3

W29 1.5-V SSTL Class I Address bus

DDR3B_A4

U23 1.5-V SSTL Class I Address bus

DDR3B_A5

AA30 1.5-V SSTL Class I Address bus

DDR3B_A6

R23 1.5-V SSTL Class I Address bus

DDR3B_A7

AC30 1.5-V SSTL Class I Address bus

DDR3B_A8

T23 1.5-V SSTL Class I Address bus

DDR3B_A9

AB29 1.5-V SSTL Class I Address bus

DDR3B_A10

R30 1.5-V SSTL Class I Address bus

DDR3B_A11

R26 1.5-V SSTL Class I Address bus

DDR3B_A12

T25 1.5-V SSTL Class I Address bus

DDR3B_A13

AD29 1.5-V SSTL Class I Address bus

DDR3B_BA0

W30 1.5-V SSTL Class I Bank address bus

DDR3B_BA1

T24 1.5-V SSTL Class I Bank address bus

DDR3B_BA2

V30 1.5-V SSTL Class I Bank address bus

DDR3B_CASN

T30 1.5-V SSTL Class I Row address select

DDR3B_CKE

L28 1.5-V SSTL Class I Column address select

DDR3B_CLK_N

P22 1.5-V SSTL Class I Differential output clock

DDR3B_CLK_P

P23 1.5-V SSTL Class I Differential output clock

DDR3B_CSN

U29 1.5-V SSTL Class I Chip select

DDR3B_DM4

P29 1.5-V SSTL Class I Write mask byte lane

DDR3B_DQ32

P28 1.5-V SSTL Class I Data bus byte lane 4

DDR3B_DQ33

K28 1.5-V SSTL Class I Data bus byte lane 4

DDR3B_DQ34

M27 1.5-V SSTL Class I Data bus byte lane 4

DDR3B_DQ35

P30 1.5-V SSTL Class I Data bus byte lane 4

DDR3B_DQ36

N29 1.5-V SSTL Class I Data bus byte lane 4

DDR3B_DQ37

M29 1.5-V SSTL Class I Data bus byte lane 4

DDR3B_DQ38

R27 1.5-V SSTL Class I Data bus byte lane 4

DDR3B_DQ39

N30 1.5-V SSTL Class I Data bus byte lane 4

DDR3B_DQS_N4

R25

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 4

DDR3B_DQS_P4

P25

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 4

DDR3B_ODT

V29 1.5-V SSTL Class I On-die termination enable

DDR3B_RASN

T29 1.5-V SSTL Class I Row address select

DDR3B_RESETN

AB27 1.5-V SSTL Class I Reset

DDR3B_WEN

T28 1.5-V SSTL Class I Write enable

DDR3B_ZQ05

— 1.5-V SSTL Class I ZQ impedance calibration

Table 2–30. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)

Board Reference

Schematic

Signal Name

Cyclone V GX

Pin Number

I/O Standard Description

1 2 ... 44 45 46 47 48 49 50 51 52 53 54 ... 59 60

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